Patents by Inventor Kazuyuki Tanimura

Kazuyuki Tanimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Homogeneous dual-rail logic for DPA attack resistive secure circuit design
    Patent number: 9240786
    Abstract: Homogenous dual-rail logic for DPA attack resistive secure circuit design is disclosed. According to one embodiment, an HDRL circuit comprises a primary cell and a complementary cell, wherein the complementary cell is an identical duplicate of the primary cell. The HURL circuit comprises a first set of inputs and a second set of inputs, wherein the second set of inputs are a negation of the first set of inputs. The HURL circuit has a differential power at a level that is resistive to DPA attacks.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: January 19, 2016
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Kazuyuki Tanimura, Nikil Dutt
  • HOMOGENEOUS DUAL-RAIL LOGIC FOR DPA ATTACK RESISTIVE SECURE CIRCUIT DESIGN
    Publication number: 20130293259
    Abstract: Homogenous dual-rail logic for DPA attack resistive secure circuit design is disclosed. According to one embodiment, an HDRL circuit comprises a primary cell and a complementary cell, wherein the complementary cell is an identical duplicate of the primary cell. The HDRL circuit comprises a first set of inputs and a second set of inputs, wherein the second set of inputs are a negation of the first set of inputs. The HDRL circuit has a differential power at a level that is resistive to DPA attacks.
    Type: Application
    Filed: March 11, 2013
    Publication date: November 7, 2013
    Inventors: Kazuyuki Tanimura, Nikil Dutt
  • Homogeneous dual-rail logic for DPA attack resistive secure circuit design
    Patent number: 8395408
    Abstract: Homogenous dual-rail logic for DPA attack resistive secure circuit design is disclosed. According to one embodiment, an HDRL circuit comprises a primary cell and a complementary cell, wherein the complementary cell is an identical duplicate of the primary cell. The HDRL circuit comprises a first set of inputs and a second set of inputs, wherein the second set of inputs are a negation of the first set of inputs. The HDRL circuit has a differential power at a level that is resistive to DPA attacks.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: March 12, 2013
    Assignee: Regents of The University of California
    Inventors: Kazuyuki Tanimura, Nikil Dutt
  • Homogeneous Dual-Rail Logic for DPA Attack Resistive Secure Circuit Design
    Publication number: 20120105099
    Abstract: Homogenous dual-rail logic for DPA attack resistive secure circuit design is disclosed. According to one embodiment, an HDRL circuit comprises a primary cell and a complementary cell, wherein the complementary cell is an identical duplicate of the primary cell. The HDRL circuit comprises a first set of inputs and a second set of inputs, wherein the second set of inputs are a negation of the first set of inputs. The HDRL circuit has a differential power at a level that is resistive to DPA attacks.
    Type: Application
    Filed: October 31, 2011
    Publication date: May 3, 2012
    Inventors: Kazuyuki Tanimura, Nikil Dutt