Patents by Inventor Kazuyuki Wada

Kazuyuki Wada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9007738
    Abstract: Provided is a transistor protection circuit capable of appropriately protecting a transistor even when a switching frequency is high. A transistor protection circuit according to an embodiment of the present invention is a transistor protection circuit for protecting a voltage-driven transistor that is switch-controlled by the application of a high-potential-side voltage or low-potential-side voltage of a power supply to a gate terminal of the transistor by a drive circuit. The transistor protection circuit has a power supply controller that gradually lowers the high-potential-side voltage of the power supply upon receiving a protection command for executing protection of the transistor.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: April 14, 2015
    Assignees: Sumitomo Electric Industries, Ltd., National University Corporation Toyohashi University of Technology
    Inventors: Kazuhiro Fujikawa, Nobuo Shiga, Takashi Ohira, Kazuyuki Wada, Tuya Wuren
  • Patent number: 8917142
    Abstract: A switching circuit 33 comprises a connection circuit cascade-connecting control terminals for controlling switching of n number of transistors M1-Mn via n?1 number of coils L1 respectively (n is an integer equal to or more than 2; and coils L3 respectively connected between one end of each of the transistors M1-Mn and other end of a coil L2, one end of the coil L2 being electrically connected to a DC power source. The transistors M1-Mn is sequentially switched with PWM signals inputted to an input terminal of the connection circuit. The switching circuit 33 further comprises a transistor M0 inserted at the one end or the other end of the coil L2 in cascade-connection.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: December 23, 2014
    Assignees: Sumitomo Electric Industries, Ltd., National University Corporation Toyohashi University of Technology
    Inventors: Satoshi Hatsukawa, Kazuhiro Fujikawa, Takashi Tsuno, Nobuo Shiga, Takashi Ohira, Kazuyuki Wada, Tuya Wuren, Kotaro Tanimura
  • Patent number: 8878604
    Abstract: A switching circuit according to one embodiment has: N switching elements; a connection circuit including N?1 first inductance elements that are connected in series; a second inductance element; and N third inductance elements. Control terminals of the N switching elements are connected to ends of the connection circuit and connection contacts, respectively. One end of the second inductance element is connected to a power supply. The N third inductance elements electrically connects one ends of the N switching elements and the other end of the second inductance element with each other, respectively.
    Type: Grant
    Filed: March 28, 2011
    Date of Patent: November 4, 2014
    Assignees: Sumitomo Electric Industries, Ltd., National University Corporation Toyohashi University of Technology
    Inventors: Takashi Ohira, Kazuyuki Wada, Mitsutoshi Nakata, Kazushi Sawada, Satoshi Hatsukawa, Nobuo Shiga, Kazuhiro Fujikawa
  • Patent number: 8766699
    Abstract: A switching circuit according to one embodiment includes first to fourth semiconductor switch elements. A pulse-like signal is applied to each input terminal of the switch elements such that when the first and fourth switch elements are in an ON (OFF) state, the remaining switch elements are in an OFF (ON) state. The switching circuit includes first and second capacitance elements. The first capacitance elements connected between an output terminal of the second semiconductor switch element and the second capacitance elements connected between an input terminal of the second semiconductor switch element and an output terminal of the fourth semiconductor switch element has a capacitance to reduce a parasitic capacitance between the input and output terminals of each of the fourth and second switch elements at a frequency N times (N is an integer of 1 or more) as high as a clock frequency of the pulse-like signal.
    Type: Grant
    Filed: June 6, 2012
    Date of Patent: July 1, 2014
    Assignees: Sumitomo Electric Industries, Ltd., National University Corporation Toyohashi University of Technology
    Inventors: Kazuhiro Fujikawa, Nobuo Shiga, Takashi Ohira, Kazuyuki Wada, Hiroshi Ishioka
  • Patent number: 8760223
    Abstract: A switching circuit according to one embodiment is a switching circuit including at least one semiconductor switch element having an input, output, and a common terminals, a pulse-like signal being applied between the input and common terminals to switch a current between the output and common terminals. The switching circuit further includes a capacitance suppression element section connected at least one of between the input and output terminals, between the input terminal common terminals, and between the output and common terminals. The capacitance suppression element section reduces a parasitic capacitance between the terminals of the semiconductor switch element where the capacitance suppression element section is connected to less than that obtained when the capacitance suppression element section is not connected at a frequency N times (N is an integer of 1 or more) as high as a clock frequency of the pulse-like signal.
    Type: Grant
    Filed: June 6, 2012
    Date of Patent: June 24, 2014
    Assignees: Sumitomo Electric Industries, Ltd., National University Corporation Toyohashi University of Technology
    Inventors: Kazuhiro Fujikawa, Nobuo Shiga, Takashi Ohira, Kazuyuki Wada, Hiroshi Ishioka
  • Patent number: 8536930
    Abstract: A switching circuit according to one embodiment includes: a switching element that has a first terminal and a second terminal, and is driven by a pulse signal to switch a conduction state between the first and second terminals; a power source section that supplies a voltage to the first terminal; a load circuit that is connected in parallel with the power source section; a passive circuit section that is connected between a connection point between the power source section and the load circuit, and the first terminal, and suppresses a current flowing from the connection point to the switching element at a frequency N times (N is an integer of 1 or more) as high as a clock frequency of the pulse signal; and a resonant circuit section that is connected between the passive circuit section and the connection point, and resonates at the frequency of N times.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: September 17, 2013
    Assignees: Sumitomo Electric Industries, Ltd., National University Corporation Toyohashi University of Technology
    Inventors: Satoshi Hatsukawa, Nobuo Shiga, Kazuhiro Fujikawa, Takashi Ohira, Kazuyuki Wada, Tuya Wuren, Kazushi Sawada, Hiroshi Ishioka
  • Publication number: 20130049862
    Abstract: A switching circuit according to one embodiment has: N switching elements; a connection circuit including N?1 first inductance elements that are connected in series; a second inductance element; and N third inductance elements. Control terminals of the N switching elements are connected to ends of the connection circuit and connection contacts, respectively. One end of the second inductance element is connected to a power supply. The N third inductance elements electrically connects one ends of the N switching elements and the other end of the second inductance element with each other, respectively.
    Type: Application
    Filed: March 28, 2011
    Publication date: February 28, 2013
    Applicants: National University Corporation TOYOHASHI UNIVERSITY OF TECHNOLOGY, Sumitomo Electric Industries, Ltd.
    Inventors: Takashi Ohira, Kazuyuki Wada, Mitsutoshi Nakata, Kazushi Sawada, Satoshi Hatsukawa, Nobuo Shiga, Kazuhiro Fujikawa
  • Publication number: 20120326774
    Abstract: A switching circuit according to one embodiment includes: a switching element that has a first terminal and a second terminal, and is driven by a pulse signal to switch a conduction state between the first and second terminals; a power source section that supplies a voltage to the first terminal; a load circuit that is connected in parallel with the power source section; a passive circuit section that is connected between a connection point between the power source section and the load circuit, and the first terminal, and suppresses a current flowing from the connection point to the switching element at a frequency N times (N is an integer of 1 or more) as high as a clock frequency of the pulse signal; and a resonant circuit section that is connected between the passive circuit section and the connection point, and resonates at the frequency of N times.
    Type: Application
    Filed: June 27, 2012
    Publication date: December 27, 2012
    Applicants: National University Corporation TOYOHASHI UNIVERSITY OF TECHNOLOGY, Sumitomo Electric Industries, Ltd.
    Inventors: Satoshi HATSUKAWA, Nobuo SHIGA, Kazuhiro FUJIKAWA, Takashi OHIRA, Kazuyuki WADA, Tuya WUREN, Kazuya ISHIOKA, Kazushi SAWADA, Hiroshi Ishioka
  • Publication number: 20120306563
    Abstract: A switching circuit according to one embodiment is a switching circuit including at least one semiconductor switch element having an input, output, and a common terminals, a pulse-like signal being applied between the input and common terminals to switch a current between the output and common terminals. The switching circuit further includes a capacitance suppression element section connected at least one of between the input and output terminals, between the input terminal common terminals, and between the output and common terminals. The capacitance suppression element section reduces a parasitic capacitance between the terminals of the semiconductor switch element where the capacitance suppression element section is connected to less than that obtained when the capacitance suppression element section is not connected at a frequency N times (N is an integer of 1 or more) as high as a clock frequency of the pulse-like signal.
    Type: Application
    Filed: June 6, 2012
    Publication date: December 6, 2012
    Applicants: National University Corporation TOYOHASHI UNIVERSITY OF TECHNOLOGY, Sumitomo Electric Industries, Ltd.
    Inventors: Kazuhiro FUJIKAWA, Nobuo Shiga, Takashi Ohira, Kazuyuki Wada, Kazuya Ishioka, Hiroshi Ishioka
  • Publication number: 20120306288
    Abstract: A switching circuit according to one embodiment includes first to fourth semiconductor switch elements. A pulse-like signal is applied to each input terminal of the switch elements such that when the first and fourth switch elements are in an ON (OFF) state, the remaining switch elements are in an OFF (ON) state. The switching circuit includes first and second capacitance elements. The first capacitance elements connected between an output terminal of the second semiconductor switch element and the second capacitance elements connected between an input terminal of the second semiconductor switch element and an output terminal of the fourth semiconductor switch element has a capacitance to reduce a parasitic capacitance between the input and output terminals of each of the fourth and second switch elements at a frequency N times (N is an integer of 1 or more) as high as a clock frequency of the pulse-like signal.
    Type: Application
    Filed: June 6, 2012
    Publication date: December 6, 2012
    Applicants: National University Corporation Toyohashi University Of Technology, Sumitomo Electric Industries, Ltd.
    Inventors: Kazuhiro Fujikawa, Nobuo Shiga, Takashi Ohira, Kazuyuki Wada, Kazuya Ishioka, Hiroshi Ishioka
  • Publication number: 20090102545
    Abstract: An input signal (Vin) is divided into n (?3) number of divided signals which are weighted by first weights (ki). The weighted divided signals are processed by n number of signal processing means 1 to n performing the same signal processing. The processed divided signals are weighted by second weights (li) and added to obtain an output signal (Vout). By selecting the first weights (ki) and the second weights (li), it is possible to eliminate noise or eliminate distortion.
    Type: Application
    Filed: April 25, 2006
    Publication date: April 23, 2009
    Inventors: Shigetaka Takagi, Nobuo Fujii, Takahide Sato, Kazuyuki Wada
  • Patent number: 6661289
    Abstract: A voltage-to-current conversion circuit composed of MOSFETs of the same polarity and an OTA with Rail-to-Rail with a simple configuration that uses the same have been disclosed. The voltage-to-current conversion circuit comprises a first MOSFET, to which a fixed drain-source voltage is applied all the time, and which generates a first current signal for an input voltage, a second MOSFET, which has the same polarity as that of the first MOSFET, to which the fixed drain-source voltage is applied all the time, and which generates a second current signal complementary to the first current signal for the input voltage, and a difference current operation circuit that performs the operation of subtraction between the first current signal and the second current signal, thereby an output current is generated in accordance with the input voltage.
    Type: Grant
    Filed: June 21, 2002
    Date of Patent: December 9, 2003
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Takahide Sato, Nobuo Fujii, Sigetaka Takagi, Kazuyuki Wada
  • Publication number: 20030071603
    Abstract: A voltage-to-current conversion circuit composed of MOSFETs of the same polarity and an OTA with Rail-to-Rail with a simple configuration that uses the same have been disclosed. The voltage-to-current conversion circuit comprises a first MOSFET, to which a fixed drain-source voltage is applied all the time, and which generates a first current signal for an input voltage, a second MOSFET, which has the same polarity as that of the first MOSFET, to which the fixed drain-source voltage is applied all the time, and which generates a second current signal complementary to the first current signal for the input voltage, and a difference current operation circuit that performs the operation of subtraction between the first current signal and the second current signal, thereby an output current is generated in accordance with the input voltage.
    Type: Application
    Filed: June 21, 2002
    Publication date: April 17, 2003
    Applicant: SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTER
    Inventors: Takahide Sato, Nobuo Fujii, Sigetaka Takagi, Kazuyuki Wada
  • Patent number: 6388520
    Abstract: A semiconductor integrated circuit comprises an amplifier circuit including a current output amplifier, a load resistor having one end connected to an output terminal of the current output amplifier and a voltage control circuit having an input terminal connected to the one end of the load resistor and an output terminal connected to an other end of the load resistor. The input terminal of the amplifier circuit serves as an input terminal of the current output amplifier, and the output terminals of the amplifier circuit serve as the individual ends of the load resistor.
    Type: Grant
    Filed: December 19, 2000
    Date of Patent: May 14, 2002
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Kazuyuki Wada, Shigetaka Takagi, Nobuo Fujii
  • Publication number: 20010005163
    Abstract: A semiconductor integrated circuit comprises an amplifier circuit including a current output amplifier, a load resistor having one end connected to an output terminal of the current output amplifier and a voltage control circuit having an input terminal connected to the one end of the load resistor and an output terminal connected to an other end of the load resistor. The input terminal of the amplifier circuit serves as an input terminal of the current output amplifier, and the output terminals of the amplifier circuit serve as the individual ends of the load resistor.
    Type: Application
    Filed: December 19, 2000
    Publication date: June 28, 2001
    Applicant: Semiconductor Technology Academic Research Center
    Inventors: Kazuyuki Wada, Shigetaka Takagi, Nobuo Fujii