Abstract: A protocol transparent retimer circuit monitors certain link layer control signals, detects far-end receiver parameters of the link partners, and detects attributes of the data signal on the link to determine the link status and operate the retimer in accordance with the determined link status. By combining and reducing host and device system states into a few retimer states, the retimer circuit is largely simplified and yet still serves its purpose. The retimer includes a controller that employs a state machine to interpret the monitored and detected signals to determine the link state and operate the retimer in an operational state corresponding to the determined link state. The approach enables the retimer to restore signal integrity and forward data it receives in both downstream and upstream directions of the link without frequency alteration.

Abstract: A protocol transparent retimer circuit monitors certain link layer control signals, detects far-end receiver parameters of the link partners, and detects attributes of the data signal on the link to determine the link status and operate the retimer in accordance with the determined link status. By combining and reducing host and device system states into a few retimer states, the retimer circuit is largely simplified and yet still serves its purpose. The retimer includes a controller that employs a state machine to interpret the monitored and detected signals to determine the link state and operate the retimer in an operational state corresponding to the determined link state. The approach enables the retimer to restore signal integrity and forward data it receives in both downstream and upstream directions of the link without frequency alteration.

Abstract: A protocol transparent retimer circuit monitors certain link layer control signals, detects far-end receiver parameters of the link partners, and detects attributes of the data signal on the link to determine the link status and operate the retimer in accordance with the determined link status. By combining and reducing host and device system states into a few retimer states, the retimer circuit is largely simplified and yet still serves its purpose. The retimer includes a controller that employs a state machine to interpret the monitored and detected signals to determine the link state and operate the retimer in an operating state corresponding to the determined link state. The approach enables the retimer to restore signal integrity and forward what ever it receives in both downstream and upstream directions of the link without frequency alteration.

Abstract: A protocol transparent retimer circuit monitors certain link layer control signals, detects far-end receiver parameters of the link partners, and detects attributes of the data signal on the link to determine the link status and operate the retimer in accordance with the determined link status. By combining and reducing host and device system states into a few retimer states, the retimer circuit is largely simplified and yet still serves its purpose. The retimer includes a controller that employs a state machine to interpret the monitored and detected signals to determine the link state and operate the retimer in an operating state corresponding to the determined link state. The approach enables the retimer to restore signal integrity and forward what ever it receives in both downstream and upstream directions of the link without frequency alteration.

Abstract: A protocol transparent retimer circuit monitors certain link layer control signals, detects far-end receiver parameters of the link partners, and detects attributes of the data signal on the link to determine the link status and operate the retimer in accordance with the determined link status. By combining and reducing host and device system states into a few retimer states, the retimer circuit is largely simplified and yet still serves its purpose. The retimer includes a controller that employs a state machine to interpret the monitored and detected signals to determine the link state and operate the retimer in an operating state corresponding to the determined link state. The approach enables the retimer to restore signal integrity and forward what ever it receives in both downstream and upstream directions of the link without frequency alteration.

Abstract: A protocol transparent retimer circuit monitors certain link layer control signals, detects far-end receiver parameters of the link partners, and detects attributes of the data signal on the link to determine the link status and operate the retimer in accordance with the determined link status. By combining and reducing host and device system states into a few retimer states, the retimer circuit is largely simplified and yet still serves its purpose. The retimer includes a controller that employs a state machine to interpret the monitored and detected signals to determine the link state and operate the retimer in an operating state corresponding to the determined link state. The approach enables the retimer to restore signal integrity and forward what ever it receives in both downstream and upstream directions of the link without frequency alteration.

Abstract: A timing network for a wireless communication network includes first and second Timing Unit Board (TUB) and processor boards for processing speech channels of the radio network, each processor board having a local timer that is slave to “PSTN time” from a Public Switch Telephone Network (PSTN). The first and second TUB each alternately transmits a timing cell containing time information to each processor board over a transport network. Each processor board realigns its local timer with the time information contained in a received timing cell whenever its local timer drifts from the time information contained in the received timing cell by a predetermined time offset. When one of the TUBs fails to transmit timing cells to the processor boards or transmits timing cells containing erroneous time information, the processor boards rely on the remaining TUB for timing cells to realign their local timers.

Abstract: A Base Station Controller (BSC) that reduces the occurrence of audible noise in a Code Division Multiple Access (CDMA) radio network is provided. The BSC according to one embodiment of the present invention comprises a Media Stream Board (MSB) for compressing groups of 160 PCM speech samples from a Public Switch Telephone Network (PSTN) into vocoded frames, and a Special Purpose Board (SPB) for reformatting the vocoded frames from the MSB into over-the-air CDMA vocoded frames. The MSB and SPB each have a local timer that is slave to “PSTN time”. The BSC further comprises a Timing Unit Board (TUB) connected to a GPS receiver. The TUB receives “GPS time” from the GPS receiver. The TUB generates timing cells, each containing time-of-day information according to “GPS time”. The TUB distributes the timing cells to the MSB and the SPB over an Asynchronous Transfer Mode (ATM) network. The MSB and SPB use the received timing cells to compare their local timer, which tracks “PSTN time”, to “GPS time”.

Abstract: A timing network for a wireless communication network includes first and second Timing Unit Board (TUB) and processor boards for processing speech channels of the radio network, each processor board having a local timer that is slave to “PSTN time” from a Public Switch Telephone Network (PSTN). The first and second TUB each alternately transmits a timing cell containing time information to each processor board over a transport network. Each processor board realigns its local timer with the time information contained in a received timing cell whenever its local timer drifts from the time information contained in the received timing cell by a predetermined time offset. When one of the TUBs fails to transmit timing cells to the processor boards or transmits timing cells containing erroneous time information, the processor boards rely on the remaining TUB for timing cells to realign their local timers.