Abstract: A CMOS inverter has two p-channel FETs connected in series between V.sub.DD and the inverter output node, an upper FET connected to V.sub.DD and a lower FET connected to the output node. The gate of a upper FET and the gate of the inverter n-channel FET are connected to the circuit input through a series FET that protects the gate oxide of these FETs by turning off if a high voltage appears at the circuit input. The circuit is useful as a buffer that receives binary voltages that may be higher than the binary voltages of the circuits of the same chip. The gate of the upper p-channel FET is connected to the input and turns off fully to block a leakage current that would otherwise flow when the n-channel FET is turned on but the lower p-channel FET is left partly conducting by the voltage drop across the series FET.

Abstract: A power supply voltage level sensing circuit and its application to circuits that interface with circuits that have performance characteristics that conform to universally accepted standards such as TTL, is described. An input terminal of a threshold shifting means is connected to the power supply to be detected to shift the voltage level of the power supply to a level acceptable by a Schmitt trigger. The threshold voltage level of the Schmitt is set so as to detect the range of the voltages that may be present at the power supply. The output of the Schmitt trigger is the data input to a first flip-flop. A system reset terminal provides a power-on-reset signal to a reset terminal of the first flip-flop and to the clock input of the first flip-flop through a buffer circuit. The power-on-reset signal maintains the output of the first flip-flop at a first level for a period of time after the activation of the power supply.

Abstract: As VLSI chip design migrates from 5 volt designs to lower voltage designs, such as 3.3 volts, interfacing components with different power supplies is an unavoidable issue. This invention provides simple and inexpensive circuits which will pass the voltage at the output node of a CMOS buffer circuit to the isolation well of the P channel metal oxide semiconductor field effect transistor in the buffer circuit when the voltage at the output node is greater than the voltage at the buffer voltage supply node. This prevents forward biasing the PN junction in the isolation well of the P channel metal oxide semiconductor field effect transistor. The circuits also provide the proper voltage level to the gate of the P channel field effect transistor.