Abstract: An analog-to-digital converting system with automatic gain control. The analog-to-digital converting system includes a programmable gain amplifier (PGA) for receiving and amplifying an input signal by a gain factor to generate an amplified input signal; an ADC, coupled to the PGA, for converting the amplified input signal into a digital signal according to an actual reference voltage signal; and an automatic gain controller, coupled to the PGA and the ADC, for jointly controlling the gain factor set to the PGA and the actual reference voltage signal set to the ADC according to a hysteretic behavior.

Abstract: An analog-to-digital converting system for converting a composite video signal into a digital signal according to a synchronized clock. The analog-to-digital converting system includes an analog-to-digital converter (ADC), a color burst phase estimator and a phase-locked loop (PLL). The ADC converts the composite video signal to the digital signal according to the synchronized clock, wherein the synchronized clock is synchronized to a frequency of a color burst of a chrominance signal of the composite video signal. The color burst phase estimator, coupled to the ADC, estimates the phase of the color burst carried on the composite video signal. The PLL, coupled to the color burst phase estimator, generates the synchronized clock according to the phase of the color burst estimated by the color burst phase estimator.

Abstract: A level clamping control circuit and associated level clamping control method are provided. The level clamping control circuit includes a reference level estimator, a subtractor, a clamping computation circuit, a dithering circuit, and a digital-to-analog converter (DAC). The reference level estimator estimates a reference level of the input signal. The subtractor computes a difference between the reference level and a desired reference level to output a difference signal. The clamping computation circuit generates a first control value according to the difference signal. The dithering circuit dithers the first control value to alternately output a plurality of second control values. Finally, the DAC respectively utilizes the second control values to charge or discharge a capacitor to adjust the reference level of the input signal.

Abstract: A method and a device for equalizing mode selection are disclosed. The method comprises steps of: providing first sampling pulses in response to an equalized signal; providing second sampling pulses lagging behind the first sampling pulses for a pre-determined phase shift for sampling the equalized signal; establishing a first observing window and a second observing window according to the first sampling pulses and the second sampling pulses, so as to determine whether each of a plurality of equalizing modes is good or bad; and selecting one equalizing mode among the plurality of equalizing modes.

Abstract: A read channel apparatus is disclosed for reading data recorded on an optical storage system at a predetermined baud rate. The apparatus asynchronously samples an analog read signal generating from the optical storage system and subtracts an estimated DC offset from the asynchronous sample values to generate a sequence of asynchronous DC-removed sample values. The asynchronous DC-removed sample values are separately interpolated by two interpolators to generate a sequence of synchronous even-time sample values and a sequence of synchronous odd-time sample values respectively. The synchronous even-time and odd-time sample values are separately equalized by two equalizers in accordance with a target spectrum to generate a sequence of even-time equalized sample values and a sequence of odd-time equalized sample values respectively. A DC offset estimator generates the estimated DC offset from the even-time equalized sample values and the odd-time equalized sample values.

Abstract: A read channel apparatus is disclosed for reading data recorded on an optical storage system at a predetermined baud rate. The apparatus asynchronously samples an analog read signal generating from the optical storage system and subtracts an estimated DC offset from the asynchronous sample values to generate a sequence of asynchronous DC-removed sample values. The asynchronous DC-removed sample values are separately interpolated by two interpolators to generate a sequence of synchronous even-time sample values and a sequence of synchronous odd-time sample values respectively. The synchronous even-time and odd-time sample values are separately equalized by two equalizers in accordance with a target spectrum to generate a sequence of even-time equalized sample values and a sequence of odd-time equalized sample values respectively. A DC offset estimator generates the estimated DC offset from the even-time equalized sample values and the odd-time equalized sample values.

Abstract: A read channel apparatus is disclosed for reading data recorded on an optical storage system at a predetermined baud rate. The apparatus asynchronously samples an analog read signal generating from the optical storage system and subtracts an estimated DC offset from the asynchronous sample values to generate a sequence of asynchronous DC-removed sample values. The asynchronous DC-removed sample values are separately interpolated by two interpolators to generate a sequence of synchronous even-time sample values and a sequence of synchronous odd-time sample values respectively. The synchronous even-time and odd-time sample values are separately equalized by two equalizers in accordance with a target spectrum to generate a sequence of even-time equalized sample values and a sequence of odd-time equalized sample values respectively. A DC offset estimator generates the estimated DC offset from the even-time equalized sample values and the odd-time equalized sample values.

Abstract: An analog-to-digital converting system with automatic gain control. The analog-to-digital converting system includes a programmable gain amplifier (PGA) for receiving and amplifying an input signal by a gain factor to generate an amplified input signal; an ADC, coupled to the PGA, for converting the amplified input signal into a digital signal according to an actual reference voltage signal; and an automatic gain controller, coupled to the PGA and the ADC, for jointly controlling the gain factor set to the PGA and the actual reference voltage signal set to the ADC according to a hysteretic behavior.

Abstract: A level clamping control circuit and associated level clamping control method are provided. The level clamping control circuit includes a reference level estimator, a subtractor, a clamping computation circuit, a dithering circuit, and a digital-to-analog converter (DAC). The reference level estimator estimates a reference level of the input signal. The subtractor computes a difference between the reference level and a desired reference level to output a difference signal. The clamping computation circuit generates a first control value according to the difference signal. The dithering circuit dithers the first control value to alternately output a plurality of second control values. Finally, the DAC respectively utilizes the second control values to charge or discharge a capacitor to adjust the reference level of the input signal.

Abstract: An analog-to-digital converting system for converting a composite video signal into a digital signal according to a synchronized clock. The analog-to-digital converting system includes an analog-to-digital converter (ADC), a color burst phase estimator and a phase-locked loop (PLL). The ADC converts the composite video signal to the digital signal according to the synchronized clock, wherein the synchronized clock is synchronized to a frequency of a color burst of a chrominance signal of the composite video signal. The color burst phase estimator, coupled to the ADC, estimates the phase of the color burst carried on the composite video signal. The PLL, coupled to the color burst phase estimator, generates the synchronized clock according to the phase of the color burst estimated by the color burst phase estimator.

Abstract: A method and a device for equalizing mode selection are disclosed. The method comprises steps of: providing first sampling pulses in response to an equalized signal; providing second sampling pulses lagging behind the first sampling pulses for a pre-determined phase shift for sampling the equalized signal; establishing a first observing window and a second observing window according to the first sampling pulses and the second sampling pulses, so as to determine whether each of a plurality of equalizing modes is good or bad; and selecting one equalizing mode among the plurality of equalizing modes.

Abstract: A read channel apparatus is disclosed for reading data recorded on an optical storage system at a predetermined baud rate. The apparatus asynchronously samples an analog read signal generating from the optical storage system and subtracts an estimated DC offset from the asynchronous sample values to generate a sequence of asynchronous DC-removed sample values. The asynchronous DC-removed sample values are separately interpolated by two interpolators to generate a sequence of synchronous even-time sample values and a sequence of synchronous odd-time sample values respectively. The synchronous even-time and odd-time sample values are separately equalized by two equalizers in accordance with a target spectrum to generate a sequence of even-time equalized sample values and a sequence of odd-time equalized sample values respectively. A DC offset estimator generates the estimated DC offset from the even-time equalized sample values and the odd-time equalized sample values.

Abstract: A read channel apparatus is disclosed for reading data recorded on an optical storage system at a predetermined baud rate. The apparatus asynchronously samples an analog read signal generating from the optical storage system and subtracts an estimated DC offset from the asynchronous sample values to generate a sequence of asynchronous DC-removed sample values. The asynchronous DC-removed sample values are separately interpolated by two interpolators to generate a sequence of synchronous even-time sample values and a sequence of synchronous odd-time sample values respectively. The synchronous even-time and odd-time sample values are separately equalized by two equalizers in accordance with a target spectrum to generate a sequence of even-time equalized sample values and a sequence of odd-time equalized sample values respectively. A DC offset estimator generates the estimated DC offset from the even-time equalized sample values and the odd-time equalized sample values.

Abstract: A read channel apparatus is disclosed for reading data recorded on an optical storage system at a predetermined baud rate. The apparatus asynchronously samples an analog read signal generating from the optical storage system and subtracts an estimated DC offset from the asynchronous sample values to generate a sequence of asynchronous DC-removed sample values. The asynchronous DC-removed sample values are separately interpolated by two interpolators to generate a sequence of synchronous even-time sample values and a sequence of synchronous odd-time sample values respectively. The synchronous even-time and odd-time sample values are separately equalized by two equalizers in accordance with a target spectrum to generate a sequence of even-time equalized sample values and a sequence of odd-time equalized sample values respectively. A DC offset estimator generates the estimated DC offset from the even-time equalized sample values and the odd-time equalized sample values.

Abstract: A DC offset cancellation circuit comprises a subtracter, a noise shaper, an accumulator and an attenuator. The subtracter is used to subtract a quantized DC offset from a digital signal. The noise shaper converts an unquantized DC offset into the quantized DC offset, the quantized DC offset having fewer bits than the unquantized DC offset and an average value in the time domain that is approximately equal to the unquantized DC offset. The accumulator generates an accumulation value by means of summing the outputs of the subtracter. The attenuator is employed to multiply the accumulation value by a constant, which is less than one, and transmit the resulting initial DC offset to the subtracter.

Abstract: A bit-serial key-equation solver employs the modified Euclidean algorithm to determine an error location polynomial and an error evaluation polynomial for decoding Reed-Solomon codes. The key equation solver includes a one-bit quotient bus for bit-serially transmitting the digits of a quotient value and a plurality of processing units each of which bit-serially receives the quotient digits from the one-bit quotient bus and each of which can be configured as a serial-in parallel-out (SIPO) standard basis bit-serial multiplier. Swapping and shifting of the register contents is also bit-serial. The key equation solver needs only the standard basis.

Abstract: A digital QPSK demodulator includes a plurality of two-input-two-output (TITO) two-fold decimators where each TITO two-fold decimator operates at a rate equal to its input data rate. The in-phase I signal and the quadrature Q signal are computed in an interleaved sequence of {Q"(n), I"(n), Q"(n+1), I"(n+1), . . . } to generate Q" decimation output and I" decimation output. The TITO two-fold decimators are cascaded in a reverse order to form a programmable down-sampler which decimates the input data by factors of 1, 2, 4, 8 or more. In a first embodiment, the programmable down-sampler is coupled between a complex multiplier and an interpolator. In a second embodiment, the in-phase and quadrature signals are fed through a complex multiplier, an interpolator, then the programmable down-sampler. In the third embodiment, the in-phase and quadrature signals are fed through an interpolator, a complex multiplier, then the programmable down-sampler.