Abstract: A thin film transistor (TFT) array substrate with few processing steps and simple structure is provided, wherein merely two patterned metal layers are required and a patterned planarization layer is adopted to separate the two patterned metal layers from each other and thereby reduce power loading. In addition, the patterned planarization layer has slots to form height differences so as to separate scan lines from common electrodes to further reduce the power loading.

Abstract: A pixel structure includes a first and a second scan lines, a data line, a first insulating layer covering the first and the second scan lines and a portion of the data line and having a recess, a second insulating layer covering the first insulating layer, a capacitor electrode line covering the data line and the recess, a third insulating layer on the capacitor electrode line, a first active device electrically connected to the second scan line and the data line, a second active device electrically connected to the first active device and the first scan line, and a first and a second pixel electrodes electrically connected to the first and the second active devices, respectively. The portion of the data line and the first and the second scan lines are in the same layer. The recess is located at two sides of the portion of the data line.

Abstract: An active device array substrate including a substrate, scan lines, data lines, active devices, a first dielectric layer, a common line, a second dielectric layer, a patterned conductive layer, a third dielectric layer, and pixel electrodes is provided. At least a part of the active devices are electrically connected to the scan lines and the data lines. The first dielectric layer covers the scan lines, the data lines and the active devices. The common line is disposed on the first dielectric layer. The second dielectric layer covers the common line and the first dielectric layer. The patterned conductive layer is disposed on the second dielectric layer. The third dielectric layer covers the patterned conductive layer and the second dielectric layer. The pixel electrodes are disposed on the third dielectric layer and electrically connected to the patterned conductive layer and the active devices.

Abstract: A thin film transistor (TFT) array substrate with few processing steps and simple structure is provided, wherein merely two patterned metal layers are required and a patterned planarization layer is adopted to separate the two patterned metal layers from each other and thereby reduce power loading. In addition, the patterned planarization layer has slots to form height differences so as to separate scan lines from common electrodes to further reduce the power loading.

Abstract: The chip on film structure for a liquid crystal display is disclosed. The chip on film structure includes a film substrate, a driver chip disposed on the film substrate, a plurality of the input pad, and a plurality of output pads. The input pads and the output pads are disposed on two opposite sides of the driver chip, and are electrically connect to the driver chip respectively. Each input pad comprises an extending portion extending from the input pads to a first cutting edge respectively, and a width of the extending portion is thinner than a width of the input pad, and the extending portions are cut along the first cutting edge.

Abstract: A drive circuit includes a drive unit coupling with data lines for receiving at least one clock signal and a first enable signal to generate a drive signal to drive data lines, and a delay unit electrically coupled with the drive unit for receiving the clock signal and the first enable signal and generating a second enable signal falling subsequent to the first enable signal in a predetermined time interval.

Abstract: A pixel structure includes a first and a second scan lines, a data line, a first insulating layer covering the first and the second scan lines and a portion of the data line and having a recess, a second insulating layer covering the first insulating layer, a capacitor electrode line covering the data line and the recess, a third insulating layer on the capacitor electrode line, a first active device electrically connected to the second scan line and the data line, a second active device electrically connected to the first active device and the first scan line, and a first and a second pixel electrodes electrically connected to the first and the second active devices, respectively. The portion of the data line and the first and the second scan lines are in the same layer. The recess is located at two sides of the portion of the data line.

Abstract: An active device array substrate including a substrate, scan lines, data lines, active devices, a first dielectric layer, a common line, a second dielectric layer, a patterned conductive layer, a third dielectric layer, and pixel electrodes is provided. At least a part of the active devices are electrically connected to the scan lines and the data lines. The first dielectric layer covers the scan lines, the data lines and the active devices. The common line is disposed on the first dielectric layer. The second dielectric layer covers the common line and the first dielectric layer. The patterned conductive layer is disposed on the second dielectric layer. The third dielectric layer covers the patterned conductive layer and the second dielectric layer. The pixel electrodes are disposed on the third dielectric layer and electrically connected to the patterned conductive layer and the active devices.

Abstract: A pixel structure of a liquid crystal display panel includes a scan line, a data line, a thin film transistor (TFT), a pixel electrode, a light-shielding pattern, and a common line. The data line includes a first data line section and a second data line section composed respectively of the first material layer and second material layer and electrically connected to each other through a plurality of contact plugs. In addition, the pixel electrode is electrically connected to a drain of the TFT, and the light-shielding pattern, which is a floating metal, is disposed over the first data line section. The common line, the light-shielding pattern, and the second data line section are composed of the same material layer.

Abstract: A pixel structure of a liquid crystal display panel includes a scan line, a data line, a thin film transistor (TFT), a pixel electrode, a light-shielding pattern, and a common line. The data line includes a first data line section and a second data line section composed respectively of the first material layer and second material layer and electrically connected to each other through a plurality of contact plugs. In addition, the pixel electrode is electrically connected to a drain of the TFT, and the light-shielding pattern, which is a floating metal, is disposed over the first data line section. The common line, the light-shielding pattern, and the second data line section are composed of the same material layer.

Abstract: The chip on film structure for a liquid crystal display is disclosed. The chip on film structure includes a film substrate, a driver chip disposed on the film substrate, a plurality of the input pad, and a plurality of output pads. The input pads and the output pads are disposed on two opposite sides of the driver chip, and are electrically connect to the driver chip respectively. Each input pad comprises an extending portion extending from the input pads to a first cutting edge respectively, and a width of the extending portion is thinner than a width of the input pad, and the extending portions are cut along the first cutting edge.

Abstract: A drive circuit includes a drive unit coupling with data lines for receiving at least one clock signal and a first enable signal to generate a drive signal to drive data lines, and a delay unit electrically coupled with the drive unit for receiving the clock signal and the first enable signal and generating a second enable signal falling subsequent to the first enable signal in a predetermined time interval.