Patents by Inventor Ke-Chih Liu

Ke-Chih Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240097009
    Abstract: A semiconductor structure includes a substrate, a channel region, a gate structure, and source/drain regions. The channel region is over the substrate. The gate structure is over the channel region, and includes a high-k dielectric layer, a tungsten layer over the high-k dielectric layer, and a fluorine-containing work function layer over the tungsten layer. The source/drain regions are at opposite sides of the channel region.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chandrashekhar P. SAVANT, Tien-Wei YU, Ke-Chih LIU, Chia-Ming TSAI
  • Patent number: 11855189
    Abstract: A semiconductor device includes a substrate, a semiconductor fin, a gate structure, and source/drain structures. The semiconductor fin extends upwardly from the substrate. The gate structure is across the semiconductor fin and includes a high-k dielectric layer over the semiconductor fin, a fluorine-containing work function layer over the high-k dielectric layer and comprising fluorine, a tungsten-containing layer over the fluorine-containing work function layer, and a metal gate electrode over the tungsten-containing layer. The source/drain structures are on the semiconductor fin and at opposite sides of the gate structure.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chandrashekhar P. Savant, Tien-Wei Yu, Ke-Chih Liu, Chia-Ming Tsai
  • Patent number: 11552178
    Abstract: The present disclosure describes a method for the formation of gate stacks having two or more titanium-aluminum (TiAl) layers with different Al concentrations (e.g., different Al/Ti ratios). For example, a gate structure can include a first TiAl layer with a first Al/Ti ratio and a second TiAl layer with a second Al/Ti ratio greater than the first Al/Ti ratio of the first TiAl layer.
    Type: Grant
    Filed: October 5, 2020
    Date of Patent: January 10, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Wei Wang, Chia-Ming Tsai, Ke-Chih Liu, Chandrashekhar Prakash Savant, Tien-Wei Yu
  • Publication number: 20220320320
    Abstract: A semiconductor device includes a substrate, a semiconductor fin, a gate structure, and source/drain structures. The semiconductor fin extends upwardly from the substrate. The gate structure is across the semiconductor fin and includes a high-k dielectric layer over the semiconductor fin, a fluorine-containing work function layer over the high-k dielectric layer and comprising fluorine, a tungsten-containing layer over the fluorine-containing work function layer, and a metal gate electrode over the tungsten-containing layer. The source/drain structures are on the semiconductor fin and at opposite sides of the gate structure.
    Type: Application
    Filed: June 17, 2022
    Publication date: October 6, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chandrashekhar P. SAVANT, Tien-Wei YU, Ke-Chih LIU, Chia-Ming TSAI
  • Patent number: 11374114
    Abstract: A high-k dielectric layer is formed over a semiconductor substrate having a first trench and a second trench. A barrier layer is formed over the high-k dielectric layer. A work function layer is deposited over the barrier layer, and is patterned and removed from the second trench, exposing the barrier layer at the second trench. A precursor is deposited selectively over the barrier layer in the second trench, and deposited over the work function layer in the first trench. The precursor selectively reacts with the barrier layer to selectively etch the barrier layer, and selectively reacts with the work function layer to selectively etch a top oxidized portion of the work function layer and deposit a protective layer. The reaction products between the precursor and the barrier layer, and the reaction products between the precursor and the work function layer are removed by using an inert gas.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: June 28, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chandrashekhar P. Savant, Tien-Wei Yu, Ke-Chih Liu, Chia-Ming Tsai
  • Publication number: 20210305411
    Abstract: A high-k dielectric layer is formed over a semiconductor substrate having a first trench and a second trench. A barrier layer is formed over the high-k dielectric layer. A work function layer is deposited over the barrier layer, and is patterned and removed from the second trench, exposing the barrier layer at the second trench. A precursor is deposited selectively over the barrier layer in the second trench, and deposited over the work function layer in the first trench. The precursor selectively reacts with the barrier layer to selectively etch the barrier layer, and selectively reacts with the work function layer to selectively etch a top oxidized portion of the work function layer and deposit a protective layer. The reaction products between the precursor and the barrier layer, and the reaction products between the precursor and the work function layer are removed by using an inert gas.
    Type: Application
    Filed: March 25, 2020
    Publication date: September 30, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chandrashekhar P. SAVANT, Tien-Wei YU, Ke-Chih LIU, Chia-Ming TSAI
  • Publication number: 20210020756
    Abstract: The present disclosure describes a method for the formation of gate stacks having two or more titanium-aluminum (TiAl) layers with different Al concentrations (e.g., different Al/Ti ratios). For example, a gate structure can include a first TiAl layer with a first Al/Ti ratio and a second TiAl layer with a second Al/Ti ratio greater than the first Al/Ti ratio of the first TiAl layer.
    Type: Application
    Filed: October 5, 2020
    Publication date: January 21, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Wei WANG, Chia-Ming TSAI, Ke-Chih LIU, Chandrashekhar Prakash SAVANT, Tien-Wei YU
  • Patent number: 10797151
    Abstract: The present disclosure describes a method for the formation of gate stacks having two or more titanium-aluminum (TiAl) layers with different Al concentrations (e.g., different Al/Ti ratios). For example, a gate structure can include a first TiAl layer with a first Al/Ti ratio and a second TiAl layer with a second Al/Ti ratio greater than the first Al/Ti ratio of the first TiAl layer.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: October 6, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Wei Wang, Chia-Ming Tsai, Ke-Chih Liu, Chandrashekhar Prakash Savant, Tien-Wei Yu
  • Patent number: 10752995
    Abstract: A method includes applying a first amount of heat to a vapor region of a precursor canister, measuring an indication of saturated vapor pressure within the vapor region during the applying the first amount of heat, and applying a second amount of heat to the vapor region of the precursor canister, the second amount of heat being adjusted from the first amount of heat based on the indication of saturated vapor pressure.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: August 25, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ke-Chih Liu, Chia-Ming Tsai, Yen-Yu Chen, Yueh-Ching Pai, Yu-Min Chang
  • Publication number: 20200105894
    Abstract: The present disclosure describes a method for the formation of gate stacks having two or more titanium-aluminum (TiAl) layers with different Al concentrations (e.g., different Al/Ti ratios). For example, a gate structure can include a first TiAl layer with a first Al/Ti ratio and a second TiAl layer with a second Al/Ti ratio greater than the first Al/Ti ratio of the first TiAl layer.
    Type: Application
    Filed: June 11, 2019
    Publication date: April 2, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Wei WANG, Chia-Ming TSAI, Ke-Chih LIU, Chandrashekhar Prakash SAVANT, Tien-Wei YU
  • Publication number: 20170167027
    Abstract: A method includes applying a first amount of heat to a vapor region of a precursor canister, measuring an indication of saturated vapor pressure within the vapor region during the applying the first amount of heat, and applying a second amount of heat to the vapor region of the precursor canister, the second amount of heat being adjusted from the first amount of heat based on the indication of saturated vapor pressure.
    Type: Application
    Filed: February 24, 2017
    Publication date: June 15, 2017
    Inventors: Ke-Chih Liu, Chia-Ming Tsai, Yen-Yu Chen, Yueh-Ching Pai, Yu-Min Chang
  • Publication number: 20170170739
    Abstract: The present invention provides a solar power converter with isolated bipolar full-bridge resonant circuit. This solar power converter system of the present invention have isolated two-stage full-bridge resonant circuit having a full-bridge resonant converter unit for solar power converter among fixed by uncontrolled phase shift controlled full bridge resonant converter unit, so as to all power switches of the full bridge resonant converter unit in any load can reach zero voltage switching, not only can improve light-load efficiency, the scope for efficiency under full load variation of both improvement and helpful.
    Type: Application
    Filed: December 11, 2015
    Publication date: June 15, 2017
    Inventors: Hsuang-Chang Chiang, Kun-Feng Chen, Ke-Chih Liu, Chin-Chieh Chang
  • Patent number: 9601593
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a gate stack positioned over the semiconductor substrate. The gate stack includes a gate dielectric layer and a gate electrode over the gate dielectric layer. The semiconductor device structure includes spacers positioned over first sidewalls of the gate stack. The spacers and the gate stack surround a recess. The semiconductor device structure includes an insulating layer formed over the semiconductor substrate and surrounding the gate stack. The semiconductor device structure includes a cap layer covering the insulating layer, the spacers, and inner walls of the recess.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: March 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ke-Chih Liu, Chia-Ming Tsai, Shih-Chi Lin
  • Publication number: 20160181925
    Abstract: A bidirectional DC-DC converter applies to a charging and discharging system equipped with a battery and especially to power fluctuations arising from the charging and discharging of the battery. The bidirectional DC-DC converter has a first full-bridge switching unit, transformer, resonance unit, second full-bridge switching unit, and frequency change control module. The first full-bridge switching unit connects with a first DC power source. The transformer has a primary side connected to the first switching unit to receive a power from the first DC power source and has a secondary side connected to the second full-bridge switching unit. The resonance unit connects with the transformer's secondary-side winding and receives power to produce resonance. The second full-bridge switching unit connects with a second DC power source. The frequency change control module instructs the switching units to perform bidirectional buck-boost switching and changes the operating frequency to adjust voltage gain.
    Type: Application
    Filed: December 17, 2014
    Publication date: June 23, 2016
    Inventors: HSUANG-CHANG CHIANG, KUO-KUANG JEN, GWO-HUEI YOU, KE-CHIH LIU
  • Publication number: 20160181809
    Abstract: A grid system conducive to enhancement of power supply performance comprises a plurality of signal regulation devices are jointly connected to a load; the signal regulation devices are each connected to a DC/DC conversion circuit and a DC/AC changing circuit through a power modulation module; an input end of the DC/DC conversion circuit receives a power signal provided by a renewable power module, and then the power modulation module performs loop control on the DC/DC conversion circuit and the DC/AC changing circuit in accordance with the power signal, the load, and/or a power state of utility electricity, such that output power of the grid system maintains high stability and low distortion and attains a satisfactory power adjustment rate at a low cost so as to make good use of all power resources and thus enhance the efficiency of overall power utilization of the grid system.
    Type: Application
    Filed: December 17, 2014
    Publication date: June 23, 2016
    Inventors: HSUANG-CHANG CHIANG, KUO-KUANG JEN, GWO-HUEI YOU, KE-CHIH LIU
  • Publication number: 20160043186
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a gate stack positioned over the semiconductor substrate. The gate stack includes a gate dielectric layer and a gate electrode over the gate dielectric layer. The semiconductor device structure includes spacers positioned over first sidewalls of the gate stack. The spacers and the gate stack surround a recess. The semiconductor device structure includes an insulating layer formed over the semiconductor substrate and surrounding the gate stack. The semiconductor device structure includes a cap layer covering the insulating layer, the spacers, and inner walls of the recess.
    Type: Application
    Filed: August 8, 2014
    Publication date: February 11, 2016
    Inventors: Ke-Chih LIU, Chia-Ming TSAI, Shih-Chi LIN
  • Publication number: 20130089934
    Abstract: A system and method for controlling saturated vapor pressure of a precursor material is provided. An embodiment comprises generating a calibration curve and utilizing the calibration curve to control a temperature of the precursor material in order to control its saturated vapor pressure. Alternatively, the calibration curve may be substituted for a real time sensor which can take readings in real time and adjust the temperature and saturated vapor pressure based upon the real time readings.
    Type: Application
    Filed: October 7, 2011
    Publication date: April 11, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ke-Chih Liu, Chia-Ming Tsai, Yen-Yu Chen
  • Publication number: 20130064973
    Abstract: A system and method for conditioning a chamber is disclosed. An embodiment comprises utilizing the deposition chamber to deposit a first layer and conditioning the deposition chamber. The conditioning the deposition chamber can be performed by depositing a heterogeneous material over the first layer. The heterogeneous material can cover and encapsulate the first layer, thereby preventing particles of the first layer from breaking off and potentially landing on a substrate during a subsequent processing run.
    Type: Application
    Filed: September 9, 2011
    Publication date: March 14, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Yu Chen, Chia-Ming Tsai, Liang-Chen Chi, Jian-Yuan Chen, Ke-Chih Liu
  • Patent number: 6835903
    Abstract: The automatic locking and releasing structure for a push-pull plug of this invention includes an upper case, a bottom case, a slider and push-buttons. The bottom case is suspended therein with two symmetrically arranged slide tracks that are each provided at the inside thereof with a wedge piece. The opposing sides of the slider are each formed with a resilient retaining arm, and the slider is movably provided between the two slide tracks. The free ends of the resilient retaining arms are movably attached to the push-buttons provided at the outside of the slide tracks. As such, when one manipulates the push-buttons to move along slide slots formed in the upper case and bottom case, the slider may be retracted or extended at the same time thereby subjecting the resilient retaining arms to assume a locking or releasing state with respect to the wedge pieces.
    Type: Grant
    Filed: April 28, 2004
    Date of Patent: December 28, 2004
    Assignee: Ahoku Electronic Company
    Inventors: Ke-Chih Liu, Jeng-Je Pan, Cho-Liang Liang
  • Patent number: 6780033
    Abstract: A safety easily operable universal adaptor which mainly disposed with a safety device and a set of shutter whereupon a control rod of the safety device is displaced toward the right and left in opposition to an up and down motion of a positioning block and then forcibly limited each plug pin to keep in position so as to enable only single set of the plug pin can be protruded outwardly; the set of shutter is disposed in the inner side of an socket of an adaptor body and then push the shutter away when a plug is inserted therein, so as to insert the socket and electrically connect to a electrically conductive plate therebetween; by virtue of this arrangement, an electrified state is formed between the plug and the plug pin.
    Type: Grant
    Filed: August 23, 2002
    Date of Patent: August 24, 2004
    Assignee: Ahoku Electronic Company
    Inventor: Ke-Chih Liu