Abstract: This disclosure provides a design method for a radiator of a vehicle power module. The design method includes: selecting a plurality of specific values from the possible value ranges of the first distance D1, the second distance D2 and the radius R, respectively, to form different combinations of the plurality of specific values, performing simulation calculations on the different combinations, and obtaining a temperature rise ?Tj and a pressure drop ?Pf corresponding to each combination to form a plurality of samples; through a response surface method, fitting explicit functions of the temperature rise ?Tj and the pressure drop ?Pf with the first distance D1, the second distance D2 and the radius R as dependent variables; and through a multi-objective optimization, determining the first distance D1, the second distance D2 and the radius R with an optimization objective that the temperature rise ?Tj and the pressure drop ?Pf are simultaneously minimized.

Abstract: The present application proposes a while-drilling fiber optic communication system and method, and relates to the technical field of drilling engineering. The system includes a wellhead mechanism, a splicing mechanism above, and a releasing mechanism. A splicing drill pipe section of the splicing mechanism is connected to a wellhead drill pipe section, and its cable coiling device retracts and releases a photoelectric composite cable, and a signal passes through a photoelectric slip ring and an optical fiber in a rigid connecting rod, and then is connected to an optical fiber in a coiling box of the releasing mechanism through a wet connector. The releasing mechanism is fixed by an anchoring device to realize while-drilling continuous communication.

Abstract: The present application proposes a three-dimensional vibration fiber Bragg grating sensor for an engineering parameter sub for logging while drilling, and belongs to the technical field of fiber Bragg grating sensors. The sensor includes a hollow shell with fiber inlet and outlet ports. Three support assemblies are sequentially arranged in the shell in an axial direction, and normal directions of end faces for slots on the three support assemblies are mutually different. A bend-insensitive optical fiber sequentially passes through all the slots, grating regions are arranged on corresponding optical fiber sections, and the grating regions and the support assemblies form sensing bodies for acquiring multi-axial-direction vibration signals.

Abstract: A power semiconductor device has a power semiconductor die forming a power switch with an input pad, an output pad, and a control pad; a collector power terminal coupled to the input pad of the power switch; an auxiliary gate terminal coupled to the control pad of the power switch; an emitter power terminal; two or more inductance/resistance pairs, with each inductance/resistance pair having a common stray inductance and a resistance arranged in series between the output pad of the power switch and the emitter power terminal; and a plurality of auxiliary emitter terminals that are coupled to both sides of the inductance/resistance pairs so that one auxiliary emitter terminal is coupled to one side of one inductance/resistance pair. A control circuit for di/dt control can control the power semiconductor device. An electronic device can include the power semiconductor device and control circuit.

Abstract: A cell structure of an insulated gate bipolar transistor (IGBT) with a control gate and a carrier storage layer, is provided including: an N-type drift layer with a first surface, an active region on a second surface opposing the first and an N-type storage layer, a P-type body layer and an N-type doped layer sequentially stacked in the active region from the first to the second surface, gate trench bodies, each of which extends from the second to the first surface in a first direction perpendicular to the first surface and contacts the N-type drift layer, and each of the at least three gate trench bodies is a gate trench or a control gate trench. A sidewall of the gate trench is in contact with the active region, and a sidewall of the control gate trench is in contact with the P-type layer but not with the N-type layer.

Abstract: The present disclosure relates to an optical system for a sample processing instrument including a flow cell with a detection channel for passage and detection of a sample. The optical system includes: a laser source; a collimating device configured to collimate beam emitted from the laser source; a focusing lens configured to focus the light beam from the laser source within the detection channel; and a reshaping device disposed between the collimating device and the focusing lens and configured to reshape spot of the collimated light beam. The reshaping device includes a first prism pair including two prisms being adjustable relative to each other so that the beam of the laser source has a predetermined size in a first direction. A sample processing instrument including the above optical system and flow cell is further provided therein.

Abstract: A room-temperature-operated high-selectivity NO2 sensor device and a fabrication method thereof are provided. The room-temperature-operated high-selectivity NO2 sensor device includes an electrode substrate and a black TiO2 sensing film uniformly loaded on a surface of the electrode substrate. The fabrication method includes the following steps: adding TiO2 to a solvent to prepare a slurry; drop-coating the slurry uniformly onto an electrode substrate, and uniformly and slowly heating the electrode substrate to remove the solvent; repeating the drop-coating and heating process a plurality of times to form a TiO2 coating with a desired thickness on a surface of the electrode substrate; and vacuum-annealing the electrode substrate with the TiO2 coating to form a black TiO2 sensing film on the surface of the electrode substrate. The black TiO2 sensing film has oxygen vacancies, enabling NO2 detection at room temperature with high selectivity and humidity resistance.

Abstract: The present disclosure relates to a distribution cable assembly that has various features to enable flexible configurations to accommodate various data center configurations.

Abstract: A package structure for a power semiconductor device is provided, including: a substrate; two or more semiconductor dies on the substrate, each of the semiconductor dies includes a first power switching pad, a second power switching pad and a gate; a gate control conductive trace, a first power switching contact and a second power switching contact are further arranged on the substrate, the gate control conductive trace is connected to each of the semiconductor dies via a bonding component, and the bonding component connecting a first semiconductor die to the gate control conductive trace is sandwiched between circuit lines formed by connecting the second power switching pads of the first semiconductor die and the neighboring second semiconductor die, to second power switching contact of the substrate.

Abstract: A semiconductor device and a manufacturing method thereof is provided. The device includes a semiconductor layer having a first and second surface opposing each other; a trench gate in the semiconductor layer, extends in a first direction parallel to the first and second surface, and from the first surface to an interior of the layer, and has a gate open end distant from the second surface; a source region of a first conductivity type and a channel region of a second conductivity type, orthographic projections of the source region and the channel region on the second surface at least partially overlap with each other in a depth direction of the trench gate, the source region having a source open end distant from the second surface, and the farther the source open end is from the second surface, the smaller a width of the source open end in the second direction.

Abstract: Provided are an in-orbit real-time task processing system, method, and device based on multi-satellite collaborative computing. The system includes a ground center and a plurality of satellites. The ground center responds to instruction text of a user, determines a target satellite based on orbital trajectories of the satellites and the task location information, and sends the instruction text and the task location information to the target satellite. The target satellite collects a remote-sensing image in real-time, determines a data processing task corresponding to the instruction text through a remote-sensing large model, performs data processing on the remote-sensing image to obtain result data, and sends the result data to the ground center.

Abstract: A method for programming a memory device, a memory device, and a memory system are disclosed. The memory device includes planes. The method includes: programming the planes by using a first programming voltage incremented with a first step size, and programming at least one but not all of the planes by using a second programming voltage incremented with a second step size. The second programming voltage is greater than the first programming voltage, and the second step size is smaller than the first step size.

Abstract: A memory device includes a memory string including a first select gate transistor and memory cells, and a peripheral circuit coupled to the memory string and configured to, during a program operation on a first memory cell of the memory cells, apply a program voltage to a first word line coupled to the first memory cell, receive an interrupt signal, and in response to the interrupt signal, after applying the program voltage to the first word line, apply a first voltage to a first select line coupled to the first select gate transistor. The first voltage is greater than a threshold voltage of the first select gate transistor.

Abstract: A method of programming a memory device. The memory device includes a plurality of memory strings, each memory string including a top transistor controlled by a top select gate (TSG) and connected to a bit line (BL), a bottom transistor controlled by a bottom select gate (BSG), and memory cells between the top and bottom transistors, each memory cell connected to a word line (WL). The method includes applying program pulses to a memory cell of the memory device in a program phase, verifying a voltage value of the memory cell in a verify phase, receiving a suspend command and performing a suspend operation, applying a discharge pulse to the memory cell in a discharge phase to thereby discharge the memory cell, wherein the discharge pulse includes a voltage pulse to an unselected top select gate (TSGunsel), and suspending programming or verifying of the memory cell in a suspend phase.

Abstract: A method for programming a memory device, a memory device, and a memory system are disclosed. The memory device includes planes. The method includes: programming the planes by using a programming voltage incremented with a first step size; verifying the planes, and in response to determining that one or more planes are with a verification exception, disabling the one or more planes with the verification exception; and in response to the one or more planes with the verification exception being disabled, programming remaining one or more planes that are not disabled by using an other programming voltage incremented with a second step size less than the first step size.

Abstract: In certain aspects, a memory device includes memory cells, word lines coupled to the memory cells, and a peripheral circuit coupled to the word lines. The peripheral circuit is configured to apply first program pulses to a selected word line of the word lines in a first program operation. The first program operation includes a first number of occurrences of suspensions and a limit on a second number of the first program pulses. The peripheral circuit is also configured to apply second program pulses to the selected word line in a second program operation. The second program operation includes a third number of occurrences of suspensions and a limit on a fourth number of the second program pulses. The first number is greater than the third number, and the second number is greater than the fourth number.

Abstract: The present disclosure relates to a system that is operable to receive an execution plan and execute a control operation on one or more equipment based operations within the execution plan. The one or more operations may include a data capturing operation associated with a resource site. In one embodiment, the system may be operable to execute at least a first operation in response to a success variable of the data capturing operation indicating a successful execution of the data capturing operation. The first operation may include a quality control operation that is executed by comparing at least one characteristic of the captured data to an expected characteristic to generate quality state data. The quality state data may have one of an acceptable status and an undesirable status. In response to the quality state data indicating an acceptable status for the quality control operation, executing at least a second operation.

Abstract: A memory device is disclosed. The memory device may include a memory string and a peripheral circuit. The memory string may include a drain select gate (DSG) transistor, a plurality of memory cells, and a source select gate (SSG) transistor. The peripheral circuit may be coupled to the memory string and configured to, during a program operation on a select memory cell of the plurality of memory cells: after detecting an interrupt signal, perform a clean process that includes turning on at least one of the DSG transistor or the SSG transistor.

Abstract: A power semiconductor device has a power semiconductor die forming a power switch with an input pad, an output pad, and a control pad; a collector power terminal coupled to the input pad of the power switch; an auxiliary gate terminal coupled to the control pad of the power switch; an emitter power terminal; two or more inductance/resistance pairs, with each inductance/resistance pair having a common stray inductance and a resistance arranged in series between the output pad of the power switch and the emitter power terminal; and a plurality of auxiliary emitter terminals that are coupled to both sides of the inductance/resistance pairs so that one auxiliary emitter terminal is coupled to one side of one inductance/resistance pair. A control circuit for di/dt control can control the power semiconductor device. An electronic device can include the power semiconductor device and control circuit.

Abstract: In certain aspects, a memory device includes memory cells, word lines coupled to the memory cells, and a peripheral circuit coupled to the memory cells. The peripheral circuit is coupled to the word lines and configured to apply program pulses to a selected word line of the word lines in a program operation, obtain a number of occurrences of suspensions during the program operation, and determine a limit on a number of program pulses for the program operation based on the number of occurrences of the suspensions during the program operation.