Abstract: Provided are an in-orbit real-time task processing system, method, and device based on multi-satellite collaborative computing. The system includes a ground center and a plurality of satellites. The ground center responds to instruction text of a user, determines a target satellite based on orbital trajectories of the satellites and the task location information, and sends the instruction text and the task location information to the target satellite. The target satellite collects a remote-sensing image in real-time, determines a data processing task corresponding to the instruction text through a remote-sensing large model, performs data processing on the remote-sensing image to obtain result data, and sends the result data to the ground center.

Abstract: A method for programming a memory device, a memory device, and a memory system are disclosed. The memory device includes planes. The method includes: programming the planes by using a first programming voltage incremented with a first step size, and programming at least one but not all of the planes by using a second programming voltage incremented with a second step size. The second programming voltage is greater than the first programming voltage, and the second step size is smaller than the first step size.

Abstract: A memory device includes a memory string including a first select gate transistor and memory cells, and a peripheral circuit coupled to the memory string and configured to, during a program operation on a first memory cell of the memory cells, apply a program voltage to a first word line coupled to the first memory cell, receive an interrupt signal, and in response to the interrupt signal, after applying the program voltage to the first word line, apply a first voltage to a first select line coupled to the first select gate transistor. The first voltage is greater than a threshold voltage of the first select gate transistor.

Abstract: A method of programming a memory device. The memory device includes a plurality of memory strings, each memory string including a top transistor controlled by a top select gate (TSG) and connected to a bit line (BL), a bottom transistor controlled by a bottom select gate (BSG), and memory cells between the top and bottom transistors, each memory cell connected to a word line (WL). The method includes applying program pulses to a memory cell of the memory device in a program phase, verifying a voltage value of the memory cell in a verify phase, receiving a suspend command and performing a suspend operation, applying a discharge pulse to the memory cell in a discharge phase to thereby discharge the memory cell, wherein the discharge pulse includes a voltage pulse to an unselected top select gate (TSGunsel), and suspending programming or verifying of the memory cell in a suspend phase.

Abstract: A method for programming a memory device, a memory device, and a memory system are disclosed. The memory device includes planes. The method includes: programming the planes by using a programming voltage incremented with a first step size; verifying the planes, and in response to determining that one or more planes are with a verification exception, disabling the one or more planes with the verification exception; and in response to the one or more planes with the verification exception being disabled, programming remaining one or more planes that are not disabled by using an other programming voltage incremented with a second step size less than the first step size.

Abstract: In certain aspects, a memory device includes memory cells, word lines coupled to the memory cells, and a peripheral circuit coupled to the word lines. The peripheral circuit is configured to apply first program pulses to a selected word line of the word lines in a first program operation. The first program operation includes a first number of occurrences of suspensions and a limit on a second number of the first program pulses. The peripheral circuit is also configured to apply second program pulses to the selected word line in a second program operation. The second program operation includes a third number of occurrences of suspensions and a limit on a fourth number of the second program pulses. The first number is greater than the third number, and the second number is greater than the fourth number.

Abstract: The present disclosure relates to a system that is operable to receive an execution plan and execute a control operation on one or more equipment based operations within the execution plan. The one or more operations may include a data capturing operation associated with a resource site. In one embodiment, the system may be operable to execute at least a first operation in response to a success variable of the data capturing operation indicating a successful execution of the data capturing operation. The first operation may include a quality control operation that is executed by comparing at least one characteristic of the captured data to an expected characteristic to generate quality state data. The quality state data may have one of an acceptable status and an undesirable status. In response to the quality state data indicating an acceptable status for the quality control operation, executing at least a second operation.

Abstract: A memory device is disclosed. The memory device may include a memory string and a peripheral circuit. The memory string may include a drain select gate (DSG) transistor, a plurality of memory cells, and a source select gate (SSG) transistor. The peripheral circuit may be coupled to the memory string and configured to, during a program operation on a select memory cell of the plurality of memory cells: after detecting an interrupt signal, perform a clean process that includes turning on at least one of the DSG transistor or the SSG transistor.

Abstract: A power semiconductor device has a power semiconductor die forming a power switch with an input pad, an output pad, and a control pad; a collector power terminal coupled to the input pad of the power switch; an auxiliary gate terminal coupled to the control pad of the power switch; an emitter power terminal; two or more inductance/resistance pairs, with each inductance/resistance pair having a common stray inductance and a resistance arranged in series between the output pad of the power switch and the emitter power terminal; and a plurality of auxiliary emitter terminals that are coupled to both sides of the inductance/resistance pairs so that one auxiliary emitter terminal is coupled to one side of one inductance/resistance pair. A control circuit for di/dt control can control the power semiconductor device. An electronic device can include the power semiconductor device and control circuit.

Abstract: In certain aspects, a memory device includes memory cells, word lines coupled to the memory cells, and a peripheral circuit coupled to the memory cells. The peripheral circuit is coupled to the word lines and configured to apply program pulses to a selected word line of the word lines in a program operation, obtain a number of occurrences of suspensions during the program operation, and determine a limit on a number of program pulses for the program operation based on the number of occurrences of the suspensions during the program operation.

Abstract: A semiconductor device includes: a substrate having a front and back surface. A main junction region, a terminal region and a field cut-off region are sequentially arranged in the substrate close to the front surface. A trench is formed in the terminal region near the field cut-off region, surrounded by field limiting rings. The junction depth of rings around the trench is greater than that of rings not surrounding it. By arranging trench structures in the terminal region, the depth of ion implantation can be increased, so that a larger junction depth can be formed subsequently. The larger junction depth can reduce a peak electric field strength on the surface; the peak electric field strength shifts from the surface to the inside of silicon; and the curvature radius of the terminal P-type implantation region is increased, thereby increasing the breakdown voltage of the terminal structure.

Abstract: A semiconductor device includes an insulated-gate bipolar transistor (IGBT) structure and a metal-oxide-semiconductor (MOS) transistor structure integrated in a wafer. The MOS transistor structure is connected in parallel with the IGBT structure. A thickness of a trench insulating layer in the MOS transistor structure is less than a thickness of a trench insulating layer in the IGBT structure.

Abstract: A semiconductor device has an active area and a terminal area surrounding the active area and includes a base region, a plurality of annular subregions, an insulating layer provided with a plurality of insulating layer openings, and a first conductive layer. The plurality of annular subregions includes a first annular subregion in contact with the base region. The first annular subregion includes a plurality of annular structures in contact with each other. All the annular structures contact the first conductive layer through the corresponding insulating layer openings. The base region, the annular subregions, and the annular structures have a second conductivity type.

Abstract: A semiconductor device includes a semiconductor layer with a first and second surface. The semiconductor layer includes: a source region and gate regions. The source region includes an N-type source region, a P-type body layer, and a carrier storage layer. Each gate region includes a gate oxide layer and polysilicon. The gate oxide layer surrounds a side wall and bottom of the polysilicon. The source region is arranged between adjacent gate regions and contacts the gate oxide layers. The gate oxide layer extends to a first depth. The bottom of the polysilicon is located at a second depth away from the first surface. A part of the gate oxide layer has a constant thickness in a transverse direction and another part gradually increases thickness in the transverse direction. The third depth is within a range of a depth where the first P-type body layer is located.

Abstract: The present disclosure relates to an optical system for a sample processing instrument including a flow cell with a detection channel for passage and detection of a sample. The optical system includes: a laser source; a collimating device configured to collimate beam emitted from the laser source; a focusing lens configured to focus the light beam from the laser source within the detection channel; and a reshaping device disposed between the collimating device and the focusing lens and configured to reshape spot of the collimated light beam. The reshaping device includes a first prism pair including two prisms being adjustable relative to each other so that the beam of the laser source has a predetermined size in a first direction. A sample processing instrument including the above optical system and flow cell is further provided therein.

Abstract: A method of programming a memory device. The memory device includes a plurality of memory strings, each memory string including a top transistor controlled by a top select gate (TSG) and connected to a bit line (BL), a bottom transistor controlled by a bottom select gate (BSG), and memory cells between the top and bottom transistors, each memory cell connected to a word line (WL). The method includes applying program pulses to a memory cell of the memory device in a program phase, verifying a voltage value of the memory cell in a verify phase, receiving a suspend command and performing a suspend operation, applying a discharge pulse to the memory cell in a discharge phase to thereby discharge the memory cell, wherein the discharge pulse includes a voltage pulse to an unselected top select gate (TSGunsel), and suspending programming or verifying of the memory cell in a suspend phase.

Abstract: The present disclosure has a substrate for power semiconductor packaging and a package containing such a substrate. The substrate includes: a first metal layer for contacting with a semiconductor device, a second metal layer for contacting with a heat dissipation device, an electrical insulation layer disposed between the first metal layer and the second metal layer, and a first graphene bulk layer disposed between the electrical insulation layer and the first metal layer, a first surface of the first graphene bulk layer is in contact with a first surface of the first metal layer, and a second surface of the first graphene bulk layer opposite to the first surface is in contact with a first surface of the electrical insulation layer. Compared to the conventional substrate, the novel substrate of the present disclosure exhibits much lower thermal resistance, higher mechanical strength, and enhanced corrosion resistance.

Abstract: This disclosure describes a machine learning system that includes a contrastive learning based two-tower model for retrieval of relevant chemical reaction procedures given a query chemical reaction. The two-tower model uses attention-based transformers and neural networks to convert tokenized representations of chemical reactions and chemical reaction procedures to embeddings in a shared embedding space. Each tower can include a transformer network, a pooling layer, a normalization layer, and a neural network. The model is trained with labeled data pairs that include a chemical reaction and the text of a chemical reaction procedure for that chemical reaction. New queries can locate chemical reaction procedures for performing a given chemical reaction as well as procedures for similar chemical reactions. The architecture and training of the model make it possible to perform semantic matching based on chemical structures. The model is highly accurate providing an average recall at K=5 of 95.9%.

Abstract: This disclosure describes a machine learning system that includes a contrastive learning based two-tower model for retrieval of relevant chemical reaction procedures given a query chemical reaction. The two-tower model uses attention-based transformers and neural networks to convert tokenized representations of chemical reactions and chemical reaction procedures to embeddings in a shared embedding space. Each tower can include a transformer network, a pooling layer, a normalization layer, and a neural network. The model is trained with labeled data pairs that include a chemical reaction and the text of a chemical reaction procedure for that chemical reaction. New queries can locate chemical reaction procedures for performing a given chemical reaction as well as procedures for similar chemical reactions. The architecture and training of the model make it possible to perform semantic matching based on chemical structures. The model is highly accurate providing an average recall at K=5 of 95.9%.

Abstract: A protective case rotating shaft comprises a main rotating flap mechanism and auxiliary rotating flap mechanisms arranged at both sides of the main rotating mechanism. The auxiliary rotating flap mechanism is connected to the main rotating flap mechanism through a connecting piece, which is configured to movably connect the main rotating flap mechanism with the auxiliary rotating flap mechanism together, so that the main and the auxiliary rotating flap mechanism move around the connecting piece at fixed points to form an opening angle, and the opening angle is 0-80 degrees. The features of the application are that it is easy to assemble, has a wide range of use, has various functions, is strong and durable, and can act as a mobile bracket for electronic equipment; at the same time, it can control the protective clip at 0 degrees and 30 degrees, 45 degrees or 60 degrees to open and close.