Abstract: A semiconductor device includes an insulated-gate bipolar transistor (IGBT) structure and a metal-oxide-semiconductor (MOS) transistor structure integrated in a wafer. The MOS transistor structure is connected in parallel with the IGBT structure. A thickness of a trench insulating layer in the MOS transistor structure is less than a thickness of a trench insulating layer in the IGBT structure.

Abstract: A semiconductor device has an active area and a terminal area surrounding the active area and includes a base region, a plurality of annular subregions, an insulating layer provided with a plurality of insulating layer openings, and a first conductive layer. The plurality of annular subregions includes a first annular subregion in contact with the base region. The first annular subregion includes a plurality of annular structures in contact with each other. All the annular structures contact the first conductive layer through the corresponding insulating layer openings. The base region, the annular subregions, and the annular structures have a second conductivity type.

Abstract: A semiconductor device includes a semiconductor layer with a first and second surface. The semiconductor layer includes: a source region and gate regions. The source region includes an N-type source region, a P-type body layer, and a carrier storage layer. Each gate region includes a gate oxide layer and polysilicon. The gate oxide layer surrounds a side wall and bottom of the polysilicon. The source region is arranged between adjacent gate regions and contacts the gate oxide layers. The gate oxide layer extends to a first depth. The bottom of the polysilicon is located at a second depth away from the first surface. A part of the gate oxide layer has a constant thickness in a transverse direction and another part gradually increases thickness in the transverse direction. The third depth is within a range of a depth where the first P-type body layer is located.

Abstract: The present disclosure relates to an optical system for a sample processing instrument including a flow cell with a detection channel for passage and detection of a sample. The optical system includes: a laser source; a collimating device configured to collimate beam emitted from the laser source; a focusing lens configured to focus the light beam from the laser source within the detection channel; and a reshaping device disposed between the collimating device and the focusing lens and configured to reshape spot of the collimated light beam. The reshaping device includes a first prism pair including two prisms being adjustable relative to each other so that the beam of the laser source has a predetermined size in a first direction. A sample processing instrument including the above optical system and flow cell is further provided therein.

Abstract: A method of programming a memory device. The memory device includes a plurality of memory strings, each memory string including a top transistor controlled by a top select gate (TSG) and connected to a bit line (BL), a bottom transistor controlled by a bottom select gate (BSG), and memory cells between the top and bottom transistors, each memory cell connected to a word line (WL). The method includes applying program pulses to a memory cell of the memory device in a program phase, verifying a voltage value of the memory cell in a verify phase, receiving a suspend command and performing a suspend operation, applying a discharge pulse to the memory cell in a discharge phase to thereby discharge the memory cell, wherein the discharge pulse includes a voltage pulse to an unselected top select gate (TSGunsel), and suspending programming or verifying of the memory cell in a suspend phase.

Abstract: The present disclosure has a substrate for power semiconductor packaging and a package containing such a substrate. The substrate includes: a first metal layer for contacting with a semiconductor device, a second metal layer for contacting with a heat dissipation device, an electrical insulation layer disposed between the first metal layer and the second metal layer, and a first graphene bulk layer disposed between the electrical insulation layer and the first metal layer, a first surface of the first graphene bulk layer is in contact with a first surface of the first metal layer, and a second surface of the first graphene bulk layer opposite to the first surface is in contact with a first surface of the electrical insulation layer. Compared to the conventional substrate, the novel substrate of the present disclosure exhibits much lower thermal resistance, higher mechanical strength, and enhanced corrosion resistance.

Abstract: This disclosure describes a machine learning system that includes a contrastive learning based two-tower model for retrieval of relevant chemical reaction procedures given a query chemical reaction. The two-tower model uses attention-based transformers and neural networks to convert tokenized representations of chemical reactions and chemical reaction procedures to embeddings in a shared embedding space. Each tower can include a transformer network, a pooling layer, a normalization layer, and a neural network. The model is trained with labeled data pairs that include a chemical reaction and the text of a chemical reaction procedure for that chemical reaction. New queries can locate chemical reaction procedures for performing a given chemical reaction as well as procedures for similar chemical reactions. The architecture and training of the model make it possible to perform semantic matching based on chemical structures. The model is highly accurate providing an average recall at K=5 of 95.9%.

Abstract: This disclosure describes a machine learning system that includes a contrastive learning based two-tower model for retrieval of relevant chemical reaction procedures given a query chemical reaction. The two-tower model uses attention-based transformers and neural networks to convert tokenized representations of chemical reactions and chemical reaction procedures to embeddings in a shared embedding space. Each tower can include a transformer network, a pooling layer, a normalization layer, and a neural network. The model is trained with labeled data pairs that include a chemical reaction and the text of a chemical reaction procedure for that chemical reaction. New queries can locate chemical reaction procedures for performing a given chemical reaction as well as procedures for similar chemical reactions. The architecture and training of the model make it possible to perform semantic matching based on chemical structures. The model is highly accurate providing an average recall at K=5 of 95.9%.

Abstract: A protective case rotating shaft comprises a main rotating flap mechanism and auxiliary rotating flap mechanisms arranged at both sides of the main rotating mechanism. The auxiliary rotating flap mechanism is connected to the main rotating flap mechanism through a connecting piece, which is configured to movably connect the main rotating flap mechanism with the auxiliary rotating flap mechanism together, so that the main and the auxiliary rotating flap mechanism move around the connecting piece at fixed points to form an opening angle, and the opening angle is 0-80 degrees. The features of the application are that it is easy to assemble, has a wide range of use, has various functions, is strong and durable, and can act as a mobile bracket for electronic equipment; at the same time, it can control the protective clip at 0 degrees and 30 degrees, 45 degrees or 60 degrees to open and close.

Abstract: A protective case for a terminal unit comprises a lower supporting mechanism, an upper supporting mechanism, a flexible connecting mechanism and a protection case rotating shaft; the lower supporting mechanism is provided with a keyboard mechanism, in which a wireless charging mechanism is arranged; the protective case rotating shaft is laterally arranged on the flexible connecting mechanism, so as to movably cover the upper supporting mechanism on the keyboard mechanism, so that an opening angle of 0-70 degrees is formed between the upper supporting mechanism and the lower supporting mechanism. The present application has various functions and a wide range of use, it can realize the function of a mobile bracket, and can be used as a mobile wireless keyboard or wireless keyboard and mouse, so as to be used in conjunction with a mobile terminal, which makes the operation of the mobile terminal more convenient.

Abstract: A method of programming a memory device. The memory device includes a plurality of memory strings, each memory string including a top transistor controlled by a top select gate (TSG) and connected to a bit line (BL), a bottom transistor controlled by a bottom select gate (BSG), and memory cells between the top and bottom transistors, each memory cell connected to a word line (WL). The method includes applying program pulses to a memory cell of the memory device in a program phase, verifying a voltage value of the memory cell in a verify phase, receiving a suspend command and performing a suspend operation, applying a discharge pulse to the memory cell in a discharge phase to thereby discharge the memory cell, wherein the discharge pulse includes a voltage pulse to an unselected top select gate (TSGunsel), and suspending programming or verifying of the memory cell in a suspend phase.

Abstract: A semiconductor device having cells is provided, with each cell including a gate. The device includes a gate pad, a gate busbar and gate lines. The busbar connects the gate pad to the gate lines, the gate lines connect the gate busbar to the gates of the cells, and each of the gate lines is disposed along a first axis. The gate busbar includes first portions each disposed along a second axis, and the second axis intersects with the first axis. The first portions are spaced apart from each other to divide the semiconductor device into emitter segments. Lengths of the emitter segments along the first axis changes with distances of the segments from the gate pad, so that gate signals arriving at the gates of the cells from the gate pad via the gate busbar and the gate lines are substantially consistent.

Abstract: A semiconductor device having cells is provided, with each cell including a gate. The device includes a gate pad, a gate busbar and gate lines. The busbar connects the gate pad to the gate lines, the gate lines connect the gate busbar to the gates of the cells, and each of the gate lines is disposed along a first axis. The gate busbar includes first portions each disposed along a second axis, and the second axis intersects with the first axis. The first portions are spaced apart from each other to divide the semiconductor device into emitter segments. Lengths of the emitter segments along the first axis changes with distances of the segments from the gate pad, so that gate signals arriving at the gates of the cells from the gate pad via the gate busbar and the gate lines are substantially consistent.

Abstract: In certain aspects, a memory device includes memory cells, word lines coupled to the memory cells, and a peripheral circuit coupled to the memory cells. The peripheral circuit is coupled to the word lines and configured to apply program pulses to a selected word line of the word lines in a program operation, obtain a number of occurrences of suspensions during the program operation, and determine a limit on a number of program pulses for the program operation based on the number of occurrences of the suspensions during the program operation.

Abstract: The present disclosure relates to a distribution cable assembly that has various features to enable flexible configurations to accommodate various data center configurations.

Abstract: In certain aspects, a memory device includes a memory string including a drain select gate (DSG) transistor, a plurality of memory cells, and a source select gate (SSG) transistor, and a peripheral circuit coupled to the memory string. The peripheral circuit is configured to in response to an interrupt during a program operation on a select memory cell of the plurality of memory cells, turn on at least one of the DSG transistor or the SSG transistor. The peripheral circuit is also configured to suspend the program operation after turning on the at least one of the DSG transistor or the SSG transistor.

Abstract: In certain aspects, a memory device includes memory cells, and a peripheral circuit coupled to the memory cells. The peripheral circuit is configured to initiate a program operation on a selected memory cell of the memory cells, obtain a number of occurrences of one or more suspensions during the program operation, and determine a program pulse limit for the program operation based on the number of occurrences of the suspensions.

Abstract: A cell structure of an insulated gate bipolar transistor (IGBT) with a control gate and a carrier storage layer, is provided including: an N-type drift layer with a first surface, an active region on a second surface opposing the first and an N-type storage layer, a P-type body layer and an N-type doped layer sequentially stacked in the active region from the first to the second surface, gate trench bodies, each of which extends from the second to the first surface in a first direction perpendicular to the first surface and contacts the N-type drift layer, and each of the at least three gate trench bodies is a gate trench or a control gate trench. A sidewall of the gate trench is in contact with the active region, and a sidewall of the control gate trench is in contact with the P-type layer but not with the N-type layer.

Abstract: The disclosure provides power semiconductor modules and their assembling methods. The module includes a heat-dissipation contact area, a housing and a press-on element. One of the housing and the press-on element includes a rail portion, while the other includes a rail cooperating portion. The housing and the press-on element respectively includes a first limiting portion and a first limiting cooperating portion. The rail cooperating portion can be inserted into the rail portion and slides on the rail portion in the direction toward or away from the plane where the heat-dissipation contact area is located, so that the press-on element could move from the separation position to the mounted position connected with the housing. The rail portion can cooperate with the rail cooperating portion to prevent the press-on element from moving relative to the housing in the direction parallel to the plane where the heat-dissipation contact area is located.