Patents by Inventor Ke-Jing Yu

Ke-Jing Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250126819
    Abstract: A semiconductor device structure and methods of forming the same are described. In some embodiments, the structure includes a first region including a gate electrode disposed over a semiconductor fin, a second region, and a border region disposed between the first and second regions. The border region includes a metal-insulator-metal (MIM) structure, and the MIM structure includes a first conductive layer disposed over the semiconductor fin, a first dielectric layer in contact with the first conductive layer, and a second conductive layer in contact with the first dielectric layer. A top surface of the second conductive layer and a top surface of the gate electrode may be substantially co-planar.
    Type: Application
    Filed: October 13, 2023
    Publication date: April 17, 2025
    Inventors: Ke-Jing YU, Yen-Liang LIN, Ru-Shang HSIAO
  • Publication number: 20250089275
    Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate and a capacitor structure. The capacitor structure is disposed on the substrate. The capacitor structure includes a first electrode and a plurality of second electrodes. At least one of the plurality of second electrodes is embedded within the first electrode.
    Type: Application
    Filed: January 2, 2024
    Publication date: March 13, 2025
    Inventors: Hui-Hung Shen, Ke-Jing Yu, Yu-Chen Chang, Anhao Cheng, Yen-Liang Lin, Ru-Shang Hsiao
  • Publication number: 20250054764
    Abstract: A semiconductor structure includes a substrate with fin features extending along a first direction; a plurality of gate stacks and a plurality of dummy pillars. The gate stacks are deposited over the substrate and extend along a second direction different from the first direction to cover the sidewalls and top surfaces of the fin features exposed from the substrate. Each gate stack includes a first gate region, a second gate region and a central region formed between the first gate region and the second gate region without covering the fin features. The dummy pillars are formed in the gate stacks besides the fin features and/or on the fin features.
    Type: Application
    Filed: August 11, 2023
    Publication date: February 13, 2025
    Inventors: KE-JING YU, YU-CHEN CHANG, ANHAO CHENG, YEN-LIANG LIN, RU-SHANG HSIAO
  • Publication number: 20250022870
    Abstract: A method is provided. The method includes the following steps: identifying a first intellectual property (IP) block and a second IP block in an integrated circuit; identifying a small border region between the first IP block and the second IP block, wherein the small border region has a width in a first horizontal direction, and the width is between a small border region dimension lower limit and a small border region dimension upper limit; and inserting at least one small dummy gate feature pattern in the small border region.
    Type: Application
    Filed: July 11, 2023
    Publication date: January 16, 2025
    Inventors: Anhao Cheng, Ke-Jing Yu, Meng-I Kang, Yen-Liang Lin, Ching Lee, Pi-Tzu Chen
  • Publication number: 20240339356
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate electrode layer formed over a substrate, and a first insulating capping feature formed over the gate electrode layer. The semiconductor device structure includes a source/drain contact structure formed adjacent to the gate electrode layer and a second insulating capping feature formed over the source/drain contact structure. The second insulating capping feature and the first insulating capping feature are made of different materials, and an air gap directly below and in direct contact with the second insulating capping feature.
    Type: Application
    Filed: June 17, 2024
    Publication date: October 10, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Chiang TSAI, Fu-Hsiang SU, Ke-Jing YU, Jyh-Huei CHEN
  • Patent number: 12040225
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate electrode layer formed over a substrate, and a conductive capping feature formed on and in direct contact with the gate electrode layer. The semiconductor device structure includes a source/drain (S/D) contact structure formed over the substrate and adjacent to the gate electrode layer, and an air gap is adjacent to the S/D contact structure, and the air gap is lower than the conductive capping feature.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: July 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Chiang Tsai, Fu-Hsiang Su, Ke-Jing Yu, Jyh-Huei Chen
  • Publication number: 20240055522
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first insulating layer and first and second gate spacers in first and second openings of the first insulating layer, respectively, forming a first conductive gate stack adjacent to the first gate spacer and forming an insulating material adjacent to the second gate spacer after forming the first conductive gate stack. The method also includes covering the first conductive gate stack and the insulating material with a first insulating capping layer and a second insulating capping layer, respectively, and forming a source/drain contact structure between the first and second gate spacer layers. The top surface of the first insulating layer is higher than those of the insulating material and is substantially level with that of the first conductive gate stack.
    Type: Application
    Filed: October 25, 2023
    Publication date: February 15, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Chiang TSAI, Fu-Hsiang SU, Ke-Jing YU, Chih-Hong HWANG, Jyh-Huei CHEN
  • Patent number: 11837663
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a conductive gate stack formed over a substrate. A first gate spacer is formed adjacent to a sidewall of the conductive gate stack. A source/drain contact structure is formed adjacent to the first gate spacer. An insulating capping layer covers and is in direct contact with an upper surface of the conductive gate stack. A top width of the insulating capping layer is substantially equal to a top width of the conductive gate stack. The insulating capping layer is separated from the source/drain contact structure by the first gate spacer.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: December 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Chiang Tsai, Fu-Hsiang Su, Ke-Jing Yu, Chih-Hong Hwang, Jyh-Huei Chen
  • Publication number: 20220319906
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate electrode layer formed over a substrate, and a conductive capping feature formed on and in direct contact with the gate electrode layer. The semiconductor device structure includes a source/drain (S/D) contact structure formed over the substrate and adjacent to the gate electrode layer, and an air gap is adjacent to the S/D contact structure, and the air gap is lower than the conductive capping feature.
    Type: Application
    Filed: June 21, 2022
    Publication date: October 6, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Chiang TSAI, Fu-Hsiang SU, Ke-Jing YU, Jyh-Huei CHEN
  • Patent number: 11393717
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate electrode layer formed over a substrate, and a gate spacer adjacent to the gate electrode layer. The semiconductor device structure includes a source/drain contact structure formed over the substrate and adjacent to the gate electrode layer. An air gap is formed between the gate spacer and the source/drain contact structure, and the air gap is in direct contact with the gate spacer.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: July 19, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Chiang Tsai, Fu-Hsiang Su, Ke-Jing Yu, Jyh-Huei Chen
  • Patent number: 11355603
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a fin structure on a substrate; forming a dummy gate over the fin structure; forming spacers on sides of the dummy gate; forming a doped region within the fin structure; replacing the dummy gate with a metal gate; replacing an upper portion of the metal gate with a first dielectric layer; forming a conductive layer directly on the doped region; replacing an upper portion of the conductive layer with a second dielectric layer; removing the first dielectric layer thereby exposing a sidewall of the spacer; removing an upper portion of the spacer to thereby expose a sidewall of the second dielectric layer; removing at least a portion of the second dielectric layer to form a trench; and forming a conductive plug in the trench.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: June 7, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Hao Wu, Chia-Hao Chang, Chih-Hao Wang, Jia-Chuan You, Yi-Hsiung Lin, Zhi-Chang Lin, Chia-Hao Kuo, Ke-Jing Yu
  • Publication number: 20210359127
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a conductive gate stack formed over a substrate. A first gate spacer is formed adjacent to a sidewall of the conductive gate stack. A source/drain contact structure is formed adjacent to the first gate spacer. An insulating capping layer covers and is in direct contact with an upper surface of the conductive gate stack. A top width of the insulating capping layer is substantially equal to a top width of the conductive gate stack. The insulating capping layer is separated from the source/drain contact structure by the first gate spacer.
    Type: Application
    Filed: August 2, 2021
    Publication date: November 18, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Chiang TSAI, Fu-Hsiang SU, Ke-Jing YU, Chih-Hong HWANG, Jyh-Huei CHEN
  • Patent number: 11139203
    Abstract: A source/drain region is disposed in a substrate. A gate structure is disposed over the substrate. A gate spacer is disposed on a sidewall of the gate structure. The gate spacer and the gate structure have substantially similar heights. A via is disposed over and electrically coupled to: the source/drain region or the gate structure. A mask layer is disposed over the gate spacer. The mask layer has a greater dielectric constant than the gate spacer. A first side of the mask layer is disposed adjacent to the via. A dielectric layer is disposed on a second side of the mask layer, wherein the mask layer is disposed between the dielectric layer and the via.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: October 5, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Chiang Tsai, Ke-Jing Yu, Fu-Hsiang Su, Yi-Ju Chen, Jyh-Huei Chen
  • Patent number: 11081585
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an insulating layer over a substrate, a gate stack formed in the insulating layer, and an insulating capping layer formed in the insulating layer to cover the gate stack. The semiconductor device structure also includes a source/drain contact structure adjacent to the gate stack. The source/drain contact structure has a sidewall that is in direct contact with a sidewall of the insulating capping layer, and an upper surface that is substantially level with an upper surface of the insulating capping layer and an upper surface of the insulating layer. In addition, the semiconductor device structure includes a first via structure above and electrically connected to the gate stack and a second via structure above and electrically connected to the source/drain contact structure.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: August 3, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Chiang Tsai, Fu-Hsiang Su, Ke-Jing Yu, Chih-Hong Hwang, Jyh-Huei Chen
  • Patent number: 11018057
    Abstract: A semiconductor device includes a substrate, a first gate structure and a second gate structure over the substrate, a first hard mask on a top surface of the first gate structure, a second hard mask on the second gate structure and a third hard mask disposed between the first gate structure and the second gate structure and disposed between the first hard mask and the second hard mask. A bottom surface of the third hard mask is substantially flush with a bottom surface of the first gate structure.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: May 25, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fu-Hsiang Su, Jyh-Huei Chen, Kuo-Chiang Tsai, Ke-Jing Yu
  • Publication number: 20210043499
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate electrode layer formed over a substrate, and a gate spacer adjacent to the gate electrode layer. The semiconductor device structure includes a source/drain contact structure formed over the substrate and adjacent to the gate electrode layer. An air gap is formed between the gate spacer and the source/drain contact structure, and the air gap is in direct contact with the gate spacer.
    Type: Application
    Filed: October 23, 2020
    Publication date: February 11, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Chiang TSAI, Fu-Hsiang SU, Ke-Jing YU, Jyh-Huei CHEN
  • Patent number: 10825721
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate stack formed over a semiconductor substrate, a source/drain contact structure laterally adjacent to the gate stack, and a gate spacer formed between the gate stack and the source/drain contact structure. The semiconductor device structure also includes a first insulating capping feature covering the upper surface of the gate stack, a second insulating capping feature covering the upper surface of the source/drain contact structure, and an insulating layer covering the upper surfaces of the first insulating capping feature and the second insulating capping feature. The second insulating capping feature includes a material that is different from the material of the first insulating capping feature. The semiconductor device structure also includes a via structure passing through the insulating layer and the first insulating capping feature and electrically connected to the gate stack.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: November 3, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Chiang Tsai, Fu-Hsiang Su, Ke-Jing Yu, Jyh-Huei Chen
  • Publication number: 20200321460
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an insulating layer over a substrate, a gate stack formed in the insulating layer, and an insulating capping layer formed in the insulating layer to cover the gate stack. The semiconductor device structure also includes a source/drain contact structure adjacent to the gate stack. The source/drain contact structure has a sidewall that is in direct contact with a sidewall of the insulating capping layer, and an upper surface that is substantially level with an upper surface of the insulating capping layer and an upper surface of the insulating layer. In addition, the semiconductor device structure includes a first via structure above and electrically connected to the gate stack and a second via structure above and electrically connected to the source/drain contact structure.
    Type: Application
    Filed: June 22, 2020
    Publication date: October 8, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Chiang TSAI, Fu-Hsiang SU, Ke-Jing YU, Chih-Hong HWANG, Jyh-Huei CHEN
  • Publication number: 20200279774
    Abstract: A semiconductor device includes a substrate, a first gate structure and a second gate structure over the substrate, a first hard mask on a top surface of the first gate structure, a second hard mask on the second gate structure and a third hard mask disposed between the first gate structure and the second gate structure and disposed between the first hard mask and the second hard mask. A bottom surface of the third hard mask is substantially flush with a bottom surface of the first gate structure.
    Type: Application
    Filed: May 18, 2020
    Publication date: September 3, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fu-Hsiang Su, Jyh-Huei Chen, Kuo-Chiang Tsai, Ke-Jing Yu
  • Patent number: 10693004
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate stack over a substrate and an insulating capping layer over the gate stack. The semiconductor device structure also includes a source/drain contact structure adjacent to the gate stack and having an upper surface that is substantially level with the upper surface of the insulating capping layer. The semiconductor device structure also includes a first via structure passing through the insulating capping layer and electrically connected to the gate stack, and a second via structure above and electrically connected to the source/drain contact structure. The first via structure and the second via structure have different vertical heights.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: June 23, 2020
    Assignee: Taiwan Semiconductor Manufactruing Co., Ltd.
    Inventors: Kuo-Chiang Tsai, Fu-Hsiang Su, Ke-Jing Yu, Chih-Hong Hwang, Jyh-Huei Chen