Patents by Inventor Ke Jing
Ke Jing has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10825721Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate stack formed over a semiconductor substrate, a source/drain contact structure laterally adjacent to the gate stack, and a gate spacer formed between the gate stack and the source/drain contact structure. The semiconductor device structure also includes a first insulating capping feature covering the upper surface of the gate stack, a second insulating capping feature covering the upper surface of the source/drain contact structure, and an insulating layer covering the upper surfaces of the first insulating capping feature and the second insulating capping feature. The second insulating capping feature includes a material that is different from the material of the first insulating capping feature. The semiconductor device structure also includes a via structure passing through the insulating layer and the first insulating capping feature and electrically connected to the gate stack.Type: GrantFiled: November 5, 2018Date of Patent: November 3, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-Chiang Tsai, Fu-Hsiang Su, Ke-Jing Yu, Jyh-Huei Chen
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Publication number: 20200321460Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an insulating layer over a substrate, a gate stack formed in the insulating layer, and an insulating capping layer formed in the insulating layer to cover the gate stack. The semiconductor device structure also includes a source/drain contact structure adjacent to the gate stack. The source/drain contact structure has a sidewall that is in direct contact with a sidewall of the insulating capping layer, and an upper surface that is substantially level with an upper surface of the insulating capping layer and an upper surface of the insulating layer. In addition, the semiconductor device structure includes a first via structure above and electrically connected to the gate stack and a second via structure above and electrically connected to the source/drain contact structure.Type: ApplicationFiled: June 22, 2020Publication date: October 8, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuo-Chiang TSAI, Fu-Hsiang SU, Ke-Jing YU, Chih-Hong HWANG, Jyh-Huei CHEN
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Publication number: 20200279774Abstract: A semiconductor device includes a substrate, a first gate structure and a second gate structure over the substrate, a first hard mask on a top surface of the first gate structure, a second hard mask on the second gate structure and a third hard mask disposed between the first gate structure and the second gate structure and disposed between the first hard mask and the second hard mask. A bottom surface of the third hard mask is substantially flush with a bottom surface of the first gate structure.Type: ApplicationFiled: May 18, 2020Publication date: September 3, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Fu-Hsiang Su, Jyh-Huei Chen, Kuo-Chiang Tsai, Ke-Jing Yu
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Patent number: 10693004Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate stack over a substrate and an insulating capping layer over the gate stack. The semiconductor device structure also includes a source/drain contact structure adjacent to the gate stack and having an upper surface that is substantially level with the upper surface of the insulating capping layer. The semiconductor device structure also includes a first via structure passing through the insulating capping layer and electrically connected to the gate stack, and a second via structure above and electrically connected to the source/drain contact structure. The first via structure and the second via structure have different vertical heights.Type: GrantFiled: October 18, 2018Date of Patent: June 23, 2020Assignee: Taiwan Semiconductor Manufactruing Co., Ltd.Inventors: Kuo-Chiang Tsai, Fu-Hsiang Su, Ke-Jing Yu, Chih-Hong Hwang, Jyh-Huei Chen
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Patent number: 10658237Abstract: Semiconductor devices are provided, and includes a substrate, a first gate structure and a second gate structure over the substrate, a first hard mask on the first gate structure and a second hard mask on the second gate structure and a third hard mask. The third hard mask is disposed in a dielectric layer between the first gate structure and the second gate structure and disposed between the first hard mask and the second hard mask.Type: GrantFiled: October 30, 2018Date of Patent: May 19, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Fu-Hsiang Su, Jyh-Huei Chen, Kuo-Chiang Tsai, Ke-Jing Yu
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Publication number: 20200127105Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a fin structure on a substrate; forming a dummy gate over the fin structure; forming spacers on sides of the dummy gate; forming a doped region within the fin structure; replacing the dummy gate with a metal gate; replacing an upper portion of the metal gate with a first dielectric layer; forming a conductive layer directly on the doped region; replacing an upper portion of the conductive layer with a second dielectric layer; removing the first dielectric layer thereby exposing a sidewall of the spacer; removing an upper portion of the spacer to thereby expose a sidewall of the second dielectric layer; removing at least a portion of the second dielectric layer to form a trench; and forming a conductive plug in the trench.Type: ApplicationFiled: December 18, 2019Publication date: April 23, 2020Inventors: Wei-Hao Wu, Chia-Hao Chang, Chih-Hao Wang, Jia-Chuan You, Yi-Hsiung Lin, Zhi-Chang Lin, Chia-Hao Kuo, Ke-Jing Yu
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Publication number: 20200126857Abstract: A source/drain region is disposed in a substrate. A gate structure is disposed over the substrate. A gate spacer is disposed on a sidewall of the gate structure. The gate spacer and the gate structure have substantially similar heights. A via is disposed over and electrically coupled to: the source/drain region or the gate structure. A mask layer is disposed over the gate spacer. The mask layer has a greater dielectric constant than the gate spacer. A first side of the mask layer is disposed adjacent to the via. A dielectric layer is disposed on a second side of the mask layer, wherein the mask layer is disposed between the dielectric layer and the via.Type: ApplicationFiled: January 31, 2019Publication date: April 23, 2020Inventors: Kuo-Chiang Tsai, Ke-Jing Yu, Fu-Hsiang Su, Yi-Ju Chen, Jyh-Huei Chen
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Publication number: 20200126843Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate stack formed over a semiconductor substrate, a source/drain contact structure laterally adjacent to the gate stack, and a gate spacer formed between the gate stack and the source/drain contact structure. The semiconductor device structure also includes a first insulating capping feature covering the upper surface of the gate stack, a second insulating capping feature covering the upper surface of the source/drain contact structure, and an insulating layer covering the upper surfaces of the first insulating capping feature and the second insulating capping feature. The second insulating capping feature includes a material that is different from the material of the first insulating capping feature. The semiconductor device structure also includes a via structure passing through the insulating layer and the first insulating capping feature and electrically connected to the gate stack.Type: ApplicationFiled: November 5, 2018Publication date: April 23, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuo-Chiang TSAI, Fu-Hsiang SU, Ke-Jing YU, Jyh-Huei CHEN
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Publication number: 20200058785Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate stack over a substrate and an insulating capping layer over the gate stack. The semiconductor device structure also includes a source/drain contact structure adjacent to the gate stack and having an upper surface that is substantially level with the upper surface of the insulating capping layer. The semiconductor device structure also includes a first via structure passing through the insulating capping layer and electrically connected to the gate stack, and a second via structure above and electrically connected to the source/drain contact structure. The first via structure and the second via structure have different vertical heights.Type: ApplicationFiled: October 18, 2018Publication date: February 20, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuo-Chiang TSAI, Fu-Hsiang SU, Ke-Jing YU, Chih-Hong HWANG, Jyh-Huei CHEN
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Publication number: 20200043787Abstract: Semiconductor devices are provided, and includes a substrate, a first gate structure and a second gate structure over the substrate, a first hard mask on the first gate structure and a second hard mask on the second gate structure and a third hard mask. The third hard mask is disposed in a dielectric layer between the first gate structure and the second gate structure and disposed between the first hard mask and the second hard mask.Type: ApplicationFiled: October 30, 2018Publication date: February 6, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Fu-Hsiang Su, Jyh-Huei Chen, Kuo-Chiang Tsai, Ke-Jing Yu
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Patent number: 10522633Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a fin structure on a substrate; forming a dummy gate over the fin structure; forming spacers on sides of the dummy gate; forming a doped region within the fin structure; replacing the dummy gate with a metal gate; replacing an upper portion of the metal gate with a first dielectric layer; forming a conductive layer directly on the doped region; replacing an upper portion of the conductive layer with a second dielectric layer; removing the first dielectric layer thereby exposing a sidewall of the spacer; removing an upper portion of the spacer to thereby expose a sidewall of the second dielectric layer; removing at least a portion of the second dielectric layer to form a trench; and forming a conductive plug in the trench.Type: GrantFiled: August 7, 2017Date of Patent: December 31, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei-Hao Wu, Chia-Hao Chang, Chih-Hao Wang, Jia-Chuan You, Yi-Hsiung Lin, Zhi-Chang Lin, Chia-Hao Kuo, Ke-Jing Yu
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Publication number: 20170338319Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a fin structure on a substrate; forming a dummy gate over the fin structure; forming spacers on sides of the dummy gate; forming a doped region within the fin structure; replacing the dummy gate with a metal gate; replacing an upper portion of the metal gate with a first dielectric layer; forming a conductive layer directly on the doped region; replacing an upper portion of the conductive layer with a second dielectric layer; removing the first dielectric layer thereby exposing a sidewall of the spacer; removing an upper portion of the spacer to thereby expose a sidewall of the second dielectric layer; removing at least a portion of the second dielectric layer to form a trench; and forming a conductive plug in the trench.Type: ApplicationFiled: August 7, 2017Publication date: November 23, 2017Inventors: Wei-Hao Wu, Chia-Hao Chang, Chih-Hao Wang, Jia-Chuan You, Yi-Hsiung Lin, Zhi-Chang Lin, Chia-Hao Kuo, Ke-Jing Yu
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Patent number: 9728505Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a fin structure on a substrate; forming a dummy gate over the fin structure; forming spacers on sides of the dummy gate; forming a doped region within the fin structure; replacing the dummy gate with a metal gate; replacing an upper portion of the metal gate with a first dielectric layer; forming a conductive layer directly on the doped region; replacing an upper portion of the conductive layer with a second dielectric layer; removing the first dielectric layer thereby exposing a sidewall of the spacer; removing an upper portion of the spacer to thereby expose a sidewall of the second dielectric layer; removing at least a portion of the second dielectric layer to form a trench; and forming a conductive plug in the trench.Type: GrantFiled: November 16, 2015Date of Patent: August 8, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei-Hao Wu, Chia-Hao Chang, Chih-Hao Wang, Jia-Chuan You, Yi-Hsiung Lin, Zhi-Chang Lin, Chia-Hao Kuo, Ke-Jing Yu
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Patent number: 9720643Abstract: An audio management method and apparatus, which relate to the field of communications technologies. The method includes: when it is detected that there is a first web page audio to be automatically played, determining whether there is an audio being played and whether a priority of the first web page audio is lower than a priority of the audio being played; when yes, intercepting automatic play of the first web page audio; otherwise, playing the first web page audio. A priority of a first web page audio to be automatically played and a priority of a web page audio being played are compared to decide whether to play the first web page audio, so that the problem of a conflict between web page audios is solved, and a user is not required to perform operations one by one.Type: GrantFiled: December 26, 2013Date of Patent: August 1, 2017Assignee: Huawei Device Co., Ltd.Inventors: Yahui Wang, Ke Jing, Wenmei Gao, Shunan Fan, Xiaoqiang Lv
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Publication number: 20170141037Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a fin structure on a substrate; forming a dummy gate over the fin structure; forming spacers on sides of the dummy gate; forming a doped region within the fin structure; replacing the dummy gate with a metal gate; replacing an upper portion of the metal gate with a first dielectric layer; forming a conductive layer directly on the doped region; replacing an upper portion of the conductive layer with a second dielectric layer; removing the first dielectric layer thereby exposing a sidewall of the spacer; removing an upper portion of the spacer to thereby expose a sidewall of the second dielectric layer; removing at least a portion of the second dielectric layer to form a trench; and forming a conductive plug in the trench.Type: ApplicationFiled: November 16, 2015Publication date: May 18, 2017Inventors: Wei-Hao Wu, Chia-Hao Chang, Chih-Hao Wang, Jia-Chuan You, Yi-Hsiung Lin, Zhi-Chang Lin, Chia-Hao Kuo, Ke-Jing Yu
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Publication number: 20150319205Abstract: A method for transferring a media stream and a user equipment, where the method for transferring a media stream includes acquiring, by a browser of a first device, information about at least one second device that may be configured to present a media stream; temporarily saving each media stream acquired by the browser of the first device from a website page or a web application; marking each temporarily saved media stream; and when it is determined that a media stream selected from the marked media streams is transferred to a selected second device for presentation, parsing the selected media stream, and sending a media stream obtained by parsing to the foregoing selected second device for presentation, where the foregoing selected second device is selected according to the information about the at least one second device.Type: ApplicationFiled: July 15, 2015Publication date: November 5, 2015Inventors: Shunan Fan, Wenmei Gao, Xiaoqiang Lv, Yahui Wang, Hao Jing, Ke Jing, Bin Hu
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Publication number: 20140115485Abstract: The present invention provides a web application management method and apparatus, where the method includes: acquiring a display mark of a web application opened in a browser, an identifier of the browser, and a uniform resource locator URL of the web application; receiving a first instruction used to display a recently opened application list, and displaying the display mark of the web application in the recently opened application list according to the first instruction; and receiving a second instruction that a user selects the web application according to the recently opened application list and opening the web application corresponding to the URL according to the second instruction by using a browser corresponding to the identifier of the browser. The present invention reduces operation steps of a user and improves the switching back efficiency of the web application.Type: ApplicationFiled: December 30, 2013Publication date: April 24, 2014Applicant: Huawei Device CO.,Ltd.Inventors: Wenmei Gao, Ke Jing, Shunan Fan, Xiaoqiang Lv, Yahui Wang
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Publication number: 20140115479Abstract: An audio management method and apparatus, which relate to the field of communications technologies. The method includes: when it is detected that there is a first web page audio to be automatically played, determining whether there is an audio being played and whether a priority of the first web page audio is lower than a priority of the audio being played; when yes, intercepting automatic play of the first web page audio; otherwise, playing the first web page audio. A priority of a first web page audio to be automatically played and a priority of a web page audio being played are compared to decide whether to play the first web page audio, so that the problem of a conflict between web page audios is solved, and a user is not required to perform operations one by one.Type: ApplicationFiled: December 26, 2013Publication date: April 24, 2014Applicant: Huawei Devices Co., Ltd.Inventors: Yahui Wang, Ke Jing, Wenmei Gao, Shunan Fan, Xiaoqiang Lv