Abstract: In certain aspects, a memory device includes memory cells and a peripheral circuit coupled to the memory cells. The memory cells include a first memory cell coupled to a first word line, a second memory cell coupled to a second word line, and a target memory cell coupled to a third word line adjacent to the first and second word lines. The peripheral circuit is configured to program the target memory cell, perform a first sample read on the first memory cell to obtain a first sample value of the first memory cell, configure one or more verification parameters of the target memory cell based on the first sample value, perform a second sample read on the second memory cell to obtain a second sample value of the second memory cell, and configure one or more read parameters of the target memory cell based on the second sample value.

Abstract: The present disclosure relates to program voltage management in memory devices and systems. An example method for programming memory cells of a memory device is provided. The method includes increasing a voltage of a first word line of the memory device from a first voltage to a second voltage in a first time period. The method further includes increasing the voltage of the first word line from the second voltage to a target program voltage in a second time period. The method further includes increasing a voltage of a second word line of the memory device from a third voltage to a fourth voltage. The second word line is adjacent to the first word line. The voltage of the second word line starts to increase from the third voltage after the voltage of the first word line reaches the second.

Abstract: Implementations of the present disclosure provide a memory device and its operation method and memory system, wherein the memory device includes: a memory cell array; a plurality of word lines; a peripheral circuit coupled to the memory cell array through the plurality of word lines, wherein the peripheral circuit is configured to: in a first stage of a programming operation, apply a first voltage to a first word line and a second word line of the plurality of word lines; in a second stage of the programming operation, apply a second voltage greater than the first voltage to the first word line and the second word line; wherein the first word line and the second word line are located on a same side of a selected word line of the plurality of word lines.

Abstract: The present disclosure provides a programming method of a memory, a memory, and a memory system, and relates to the technical field of semiconductor chips. The method includes: applying a first program voltage to a first type of selected word lines and a reference voltage to unselected word lines adjacent to the first type of selected word lines during a first time period of a first program stage; and applying a second program voltage to the first type of selected word lines and a pass voltage to the unselected word lines adjacent to the first type of selected word lines during a second time period of the first program stage, wherein memory cells coupled to the unselected word lines adjacent to the first type of selected word lines are in an erased state, and the second program voltage is greater than the first program voltage.

Abstract: In certain aspects, a memory device includes an array of memory cells, word lines respectively coupled to rows of the memory cells, and a peripheral circuit coupled to the array of memory cells through the word lines. Each memory cell is set to one of 2N final levels corresponding to a piece of N-bits data, where N is an integer greater than 2. The peripheral circuit is configured to program, in a first pass, a select row of the rows of the memory cells, such that the memory cells in the selected row are set to k intermediate levels, where k is an integer not greater than 2N. The peripheral circuit is also configured to, after the first pass, apply a single voltage pulse to a select word line of the word lines coupled to the select row of the memory cells, wherein an amplitude of the single voltage pulse changes over time.

Abstract: In certain aspects, a memory device includes a block of memory cells, and a peripheral circuit coupled to the block of memory cells. The peripheral circuit is configured to, in an erase operation, pre-erase the block of memory cells, program the block of memory cells after pre-erasing the block of memory cells, and erase the block of memory cells after programming the block of memory cells.

Abstract: Example memory devices, systems, and methods for reducing verify operation time in memory devices are disclosed. One example method includes performing, based on one of 2N pieces of N-bits data, a first programming operation of the target memory cell to program the target memory cell into an intermediate threshold voltage range P 1 I of a first set of 2N-1 threshold voltage ranges { P 1 0 , P 1 1 , … , P 1 2 N - 2 } , where P 1 2 N - 2 ? and ? P 1 2 N - 3 share a same verify voltage.

Abstract: In certain aspects, a memory device includes memory cells and a peripheral circuit coupled to the memory cells. The memory cells include a first memory cell coupled to a first word line, a second memory cell coupled to a second word line, and a target memory cell coupled to a third word line adjacent to the first and second word lines. The peripheral circuit is configured to program the target memory cell, perform a first sample read on the first memory cell to obtain a first sample value of the first memory cell, configure one or more verification parameters of the target memory cell based on the first sample value, perform a second sample read on the second memory cell to obtain a second sample value of the second memory cell, and configure one or more read parameters of the target memory cell based on the second sample value.

Abstract: Provided are a complex of an anti-IL-4R antibody or an antigen-binding fragment thereof, and a medical use thereof. Specifically, provided are a complex of an antibody that specifically binds to IL-4R or an antigen-binding fragment thereof covalently linked to a toxin, a pharmaceutical composition comprising the complex, and a use thereof in the preparation of a drug for treating IL-4R-mediated diseases or disorders, especially a use in the preparation of an anti-cancer drug.

Abstract: A risk assessment-based design method for a deep complex formation wellbore structure includes: (1) preliminarily determining casing layers and setting depths; (2) calculating to obtain the risk coefficients of each layer of casing; (3) analyzing and coordinating, according to the principle that a shallow casing shares more risks and a deep casing shares less risks, the risks of each layer of casing: determining whether the risk coefficients of each layer of casing are greater than a safety threshold value K; checking the setting depth: if the safety coefficient of an ith-layer casing satisfies RNi>K, selecting a casing layer with the minimum safety coefficient from upper casing layers, and deepening the setting depth h of the casing layer; and (4) repeating the steps (2) to (3) until the casing risk coefficients of each layer of casing are less than the safety threshold value K.

Abstract: A risk assessment-based design method for a deep complex formation wellbore structure includes: (1) preliminarily determining casing layers and setting depths; (2) calculating to obtain the risk coefficients of each layer of casing; (3) analyzing and coordinating, according to the principle that a shallow casing shares more risks and a deep casing shares less risks, the risks of each layer of casing: determining whether the risk coefficients of each layer of casing are greater than a safety threshold value K; checking the setting depth: if the safety coefficient of an ith-layer casing satisfies RNi>K, selecting a casing layer with the minimum safety coefficient from upper casing layers, and deepening the setting depth h of the casing layer; and (4) repeating the steps (2) to (3) until the casing risk coefficients of each layer of casing are less than the safety threshold value K.

Abstract: Provided herein are compositions comprising distinct lipid species in defined ratios and methods of use thereof for the detection of anti-phosphatidylethanolamine (aPE) antibodies and diagnosis of antiphospholipid syndrome (APS).

Abstract: An embodiment provides a method, including: acquiring, using a processor of an electronic device, current device configuration information and past device operation behavior information; determining, using the processor, one or more traits of a target user of the electronic device based on the current device configuration information and the past operation behavior information; and recommending, via an output element of the electronic device, a device configuration to the target user based on the current device configuration information and the user traits. Other embodiments are described and claimed.

Abstract: Provided herein are compositions comprising distinct lipid species in defined ratios and methods of use thereof for the detection of anti-phosphatidylethanolamine (aPE) antibodies and diagnosis of antiphospholipid syndrome (APS).

Abstract: The present invention provides a virtual machine system and a method for sharing a graphics card amongst virtual machines. A VMM of the virtual machine system is provided with a resource-converting module, which converts data exchanged between a graphics card drive module of a GOS in the foreground and the graphics card based on a resource-converting table, and also intercepts accesses to the real graphics card by a GOS in the background and then responds to its operations on the graphics card. The VMM is further provided with a switching module, which alters a state of a VM based on a command for switching the VM, saves a graphics card state before the VM is switched to the background and restores the stored graphics card state to the graphics card when the VM is switched back to the foreground. Further, the GOSs each comprise a graphics card drive module corresponding to the real graphics card for accessing the real graphics card.

Abstract: A system and method for hybrid virtual machine monitor system is provided. A first operating system uses a file system to manage data storage and retrieval within a data storage area. A second operating system, which is not compatible with the first operating system's file system, executes a management application backup utility. The first operating system includes a filter driver that sends logical block addresses, which correspond to data reads/writes, to the management application backup utility. In turn, the management application backup utility uses the logical block addresses to perform operations on the data storage locations. In one embodiment, the management application backup utility performs actions on the data storage area, such as a disk defragmentation, and subsequently sends data location changes to the filter driver. In this embodiment, the filter driver instructs the first operating system's file system to update its translation tables based upon the data location changes.

Abstract: A computer and method for directly accessing computer hardware by a virtual system are provided. The computer comprises a hardware platform having a first-type device, a second-type device and a third-type device provided thereon; a virtual machine managing module; a first operating module; a second operating module; wherein the virtual machine managing module comprises a first-type device configuration module for directly configuring the first type device to be used by the main operating system; a second-type device configuration module for directly configuring the second-type device to be used by the guest operating system; and a third-type device configuration module for virtualizing the third-type device on the hardware platform to generate a virtualized third-type device and configuring the virtualized third-type device to be used by the main operating system and the guest operating system, respectively.

Abstract: The present invention provides a virtual machine system and a method of accessing a graphics card. The virtual machine system includes a VMM, an SOS and at least one GOS, and further includes a resource converting module for performing IO address converting on graphics card framebuffer accessing data from GOS(s) or mapping MMIO(s) to physical MMIO(s) of a graphics card based on a resource converting table, and sending the processed data to the graphics card; and a framebuffer allocating module for dividing a framebuffer resource of the graphics card into multiple blocks and allocating them respectively to corresponding GOS(s). The resource converting table(s) records correspondences between a resource allocation for the graphics card by SOS and a resource allocation for the graphics card by GOS(s). The framebuffer MMIO resource(s) allocated to the graphics card by GOS(s) is/are the framebuffer allocated to GOS(s) by the framebuffer allocating module.

Abstract: A computer and method for directly accessing computer hardware by a virtual system are provided. The computer comprises a hardware platform having a first-type device, a second-type device and a third-type device provided thereon; a virtual machine managing module; a first operating module; a second operating module; wherein the virtual machine managing module comprises a first-type device configuration module for directly configuring the first type device to be used by the main operating system; a second-type device configuration module for directly configuring the second-type device to be used by the guest operating system; and a third-type device configuration module for virtualizing the third-type device on the hardware platform to generate a virtualized third-type device and configuring the virtualized third-type device to be used by the main operating system and the guest operating system, respectively.

Abstract: The present invention provides a computer system for carrying out security reinforcing and a security reinforcing method. The computer system comprises hardware, a BIOS, and a virtual machine monitor, and has at least one servo operating system and at least one user operating system running thereon, wherein, the servo operating system comprises a security reinforcing proxy module, and the user operating system comprises a security reinforcing module. With the present invention, it is possible to prevent the security reinforcing performance from being tampered by the frangibility of the user operating system, and to avoid hacker attacks which cannot be avoided in case of regular or manual security reinforcing, and also to ensure better secure defense of the computer system and the security of the downloaded security reinforcing files own.