Abstract: Provided herein, inter alia, are compositions and kits comprising epicardial-derived paracrine factors (such as, hypoglycosylated follistatin-like 1 (FSTL1)) for treating and repairing damage to cardiac tissue caused by cardiovascular disease, myocardial infarction (MI), other ischemic events, or cardiac-growth deficiency, as well as methods for using the same.

Abstract: The present disclosure relates to the technical field of semiconductors. Disclosed is a multi-layer semiconductor material structure and a preparation method thereof, solving the problems of the existing semiconductor materials that have poor heat dissipation, high cost, and cannot be mass-produced. The multi-layer semiconductor material structure includes a highly thermally conductive support substrate and a crystallized device function layer, where the device function layer is provided on the highly thermally conductive support substrate, and has a single-crystal surface layer.

Abstract: The present disclosure relates to a data writing method and apparatus of a NAND flash, and a storage medium. The method includes: for each channel in the NAND flash, pairing all logic units, namely LUNs, in the channel so that each LUN pair includes at least two LUNs; and for each LUN pair, sequentially writing data to one same page in a plurality of pages corresponding to a program mode included in each word line of each LUN in the LUN pair, and after completing data writing to the same page of the word line of all the LUNs in the LUN pair, sequentially writing data to a next same page in the plurality of pages of the word line of each LUN in the LUN pair, until the data writing is sequentially performed on a last same page in the plurality of pages of the word line of each LUN in the LUN pair. Therefore, the transmission efficiency of a NAND bus can be improved, and the data writing performance of the NAND flash can be improved.

Abstract: The display drive circuit includes: an interface circuit for acquiring a plurality of grayscale data and a plurality of current gain data; a command processing circuit electrically coupled with the interface circuit; a cache circuit electrically coupled with the interface circuit and configured for caching the plurality of grayscale data and the plurality of current gain data; a current source circuit electrically coupled with the command processing circuit and including a plurality of channel current sources; a channel grayscale control circuit, electrically coupled with the command processing circuit, the cache circuit and the current source circuit, and configured for respectively controlling duration of turning on of the plurality of channel current sources according to the plurality of grayscale data; and a channel current control circuit electrically coupled with the cache circuit and the current source circuit, and configured for respectively controlling output currents of the plurality of channel curr

Abstract: The present disclosure relates to a data writing method and apparatus of a NAND flash, and a storage medium. The method includes: for each channel in the NAND flash, pairing all logic units, namely LUNs, in the channel so that each LUN pair includes at least two LUNs; and for each LUN pair, sequentially writing data to one same page in a plurality of pages corresponding to a program mode included in each word line of each LUN in the LUN pair, and after completing data writing to the same page of the word line of all the LUNs in the LUN pair, sequentially writing data to a next same page in the plurality of pages of the word line of each LUN in the LUN pair, until the data writing is sequentially performed on a last same page in the plurality of pages of the word line of each LUN in the LUN pair. Therefore, the transmission efficiency of a NAND bus can be improved, and the data writing performance of the NAND flash can be improved.

Abstract: The display drive circuit includes: an interface circuit configured for acquiring a plurality of grayscale data and a plurality of current gain data; a command processing circuit electrically coupled with the interface circuit; a cache circuit electrically coupled with the interface circuit and configured for caching the plurality of grayscale data and the plurality of current gain data; a current source circuit electrically coupled with the command processing circuit and including a plurality of channel current sources; a channel grayscale control circuit, electrically coupled with the command processing circuit, the cache circuit and the current source circuit, and configured for respectively controlling duration of turning on of the plurality of channel current sources according to the plurality of grayscale data; and a channel current control circuit electrically coupled with the cache circuit and the current source circuit, and configured for respectively controlling output currents of the plurality of c

Abstract: The present disclosure relates to the technical field of semiconductors. Disclosed is a multi-layer semiconductor material structure and a preparation method thereof, solving the problems of the existing semiconductor materials that have poor heat dissipation, high cost, and cannot be mass-produced. The multi-layer semiconductor material structure includes a highly thermally conductive support substrate and a crystallized device function layer, where the device function layer is provided on the highly thermally conductive support substrate, and has a single-crystal surface layer.

Abstract: The present disclosure relates to an emulation test system for flash translation layer and a method thereof, the system comprising a network block device, a virtual hardware accelerator, a flash translation layer module, and a virtual flash memory based on the network block device, wherein the network block device is configured to receive and forward test information, the test information including a read instruction and/or a write instruction and data to be written; the virtual hardware accelerator is configured to allocate the test information to each thread of the virtual hardware accelerator and perform virtual hardware acceleration on the flash translation layer module; and the flash translation layer module is configured to operate the virtual flash memory based on the test information to obtain an operation result.

Abstract: The present disclosure relates to an emulation test system for flash translation layer and a method thereof, the system comprising a network block device, a virtual hardware accelerator, a flash translation layer module, and a virtual flash memory based on the network block device, wherein the network block device is configured to receive and forward test information, the test information including a read instruction and/or a write instruction and data to be written; the virtual hardware accelerator is configured to allocate the test information to each thread of the virtual hardware accelerator and perform virtual hardware acceleration on the flash translation layer module; and the flash translation layer module is configured to operate the virtual flash memory based on the test information to obtain an operation result.

Abstract: A reading method for solid-state disk returns data and/or information depending on state information. A data unit stored in the solid-state disk comprises metadata and a plurality of sectors including at least two sectors of user data, the metadata comprising a sector state set indicating state information of each of the sectors in the data unit, and the state information comprising a valid state and an invalid state. In response to receiving a read command from a host to read at least one of the sectors in the data unit, the solid-state disk returns actual data to the host for one or more of the sectors in the valid state, and returns information indicating a read error to the host for one or more of the sectors in the invalid state, according to the sector state set stored in the metadata of the data unit.

Abstract: A reading method for solid-state disk returns data and/or information depending on state information. A data unit stored in the solid-state disk comprises metadata and a plurality of sectors including at least two sectors of user data, the metadata comprising a sector state set indicating state information of each of the sectors in the data unit, and the state information comprising a valid state and an invalid state. In response to receiving a read command from a host to read at least one of the sectors in the data unit, the solid-state disk returns actual data to the host for one or more of the sectors in the valid state, and returns information indicating a read error to the host for one or more of the sectors in the invalid state, according to the sector state set stored in the metadata of the data unit.

Abstract: A method and apparatus for determining a reference voltage id disclosed. The method may include: reading data from a first flash memory page by using different reference voltages, and taking, as a first target reference voltage, one of the different reference voltages at which the first number of erroneous bits of the data that is read reaches a converegence value. The first flash memory page is any one of multiple flash memory pages of a flash memory block to be tested. The method may include adjusting the first target reference voltage to obtain second target reference voltages; and reading data from the flash memory pages by using the second target referece voltages, and taking, as a target reference voltage, one of the second target reference voltages at which the second number of erroneous bits of the data that is read is the smallest.

Abstract: A GaN-based superjunction vertical power transistor and a manufacturing method thereof. The transistor includes: a N?-GaN layer; a first P-GaN layer as a current blocking layer, formed on the N?-GaN layer and having a gate region window; and a thin barrier Al(In, Ga)N/GaN heterostructure conformally formed on the current blocking layer and filling the bottom and one or more sidewalls of the gate region window, wherein the N?-GaN layer has an etched groove completely or partially filled with a second P-type GaN layer, an N+-GaN layer is formed under the second P-type GaN layer, and the N+-GaN layer is in direct contact with the second P-type GaN layer and the N?-GaN layer to form a superjunction composite structure.

Abstract: A GaN-based superjunction vertical power transistor and a manufacturing method thereof. The transistor includes: a N?-GaN layer; a first P-GaN layer as a current blocking layer, formed on the N?-GaN layer and having a gate region window; and a thin barrier Al(In, Ga)N/GaN heterostructure conformally formed on the current blocking layer and filling the bottom and one or more sidewalls of the gate region window, wherein the N?-GaN layer has an etched groove completely or partially filled with a second P-type GaN layer, an N+-GaN layer is formed under the second P-type GaN layer, and the N+-GaN layer is in direct contact with the second P-type GaN layer and the N?-GaN layer to form a superjunction composite structure.

Abstract: A detector based on a gallium nitride-based enhancement-mode device and a manufacturing method thereof. The detector is a gas or solution detector. When the detector is used in electrolyte solution detection, electrolyte solution is located in the gate opening region and directly contacts the thin barrier layer to form a contact interface. The electrolyte solution affects interface charges at the contact interface, leading to a change in a concentration of the two-dimensional electron gas, and further a change in a current between the source and the drain. When the detector is used in a hydrogen-containing gas detection, the H concentration of the hydrogen-containing gas affects interface charges at the contact interface between the gate and the thin barrier layer, leading to a change in a concentration of the two-dimensional electron gas, and further a change in the current between the source and the drain.

Abstract: The present disclosure relates to a method and apparatus for determining a reference voltage. The method may comprise: reading data from a first flash memory page by using a plurality of different reference voltages, and taking, as a first target reference voltage, one of the plurality of different reference voltages at which the first number of erroneous bits of the data that is read reaches a convergence value, wherein the first flash memory page is any one of a plurality of flash memory pages of a flash memory block to be tested; adjusting the first target reference voltage to obtain a plurality of second target reference voltages; and reading data from the plurality of flash memory pages of the flash memory block by using the plurality of second target reference voltages, and taking, as a target reference voltage, one of the plurality of second target reference voltages at which the second number of erroneous bits of the data that is read is the smallest.

Abstract: An electronic circuit comprises an input voltage circuit, an analog-to-digital converter (ADC) circuit, and logic circuitry. The input voltage circuit is configured to generate multiple input voltages. The ADC circuit is configured to convert the multiple input voltages to first digital values using the first longer ADC acquisition time and convert the multiple input voltages to second digital values using the second shorter ADC acquisition time. The logic circuitry is configured to determine calibration information for the ADC circuit using the first digital values and the second digital values, and scale analog-to-digital (A/D) conversion results of the ADC circuit using the calibration information.

Abstract: Provided herein, inter alia, are compositions and kits comprising epicardial-derived paracrine factors (such as, hypoglycosylated follistatin-like 1 (FSTL1)) for treating and repairing damage to cardiac tissue caused by cardiovascular disease, myocardial infarction (MI), other ischemic events, or cardiac-growth deficiency, as well as methods for using the same.

Abstract: A GaN-based enhancement-mode power electronic device and a method for manufacturing the same. The GaN-based enhancement-mode power electronic device comprises: a substrate; a thin barrier Al(In,Ga)N/GaN heterostructure formed on the substrate; a gate, a source, and a drain formed on the thin barrier Al(In,Ga)N/GaN heterostructure. An AlN or SiNx passivation layer is formed on access regions between the gate and the source and between the gate and the drain, respectively, such that two dimensional electron gas is recovered in channels of the thin barrier Al(In,Ga)N/GaN heterostructure below the MN passivation layer by utilizing the MN passivation layer having polarization characteristics, or by using the SiNx passivation layer with positive fixed bulk/interface charges, so as to reduce on-resistance of the device and inhibit high-voltage current collapse in the device.

Abstract: Provided herein, inter alia, are compositions and kits comprising epicardial-derived paracrine factors (such as, hypoglycosylated follistatin-like 1 (FSTL1)) for treating and repairing damage to cardiac tissue caused by cardiovascular disease, myocardial infarction (MI), other ischemic events, or cardiac-growth deficiency, as well as methods for using the same.