Abstract: The present invention discloses a shed tunnel structure for preventing a falling rock, including a shed tunnel body and a buffer plate for bearing impact of the falling rock, where the shed tunnel body includes a first supporting structure, and the first supporting structure is arranged on a side away from a ramp; one end of the buffer plate is connected to the ramp; a side face of the buffer plate close to the shed tunnel body is in movable contact with the first supporting structure, and the contact position is close to the other end of the buffer plate. The objective of resisting continuous impact of the falling rock can be achieved through the structural design.

Abstract: An independent graphics card system comprises an expansion motherboard, a system power supply, at least one expansion graphics card and a fan assembly. The system power supply is electrically connected to the expansion motherboard. The at least one expansion graphics card is plugged into the expansion motherboard through an adapter card. The at least one expansion graphics card is parallel with the expansion motherboard. The fan assembly dissipates heat of the at least one expansion graphics card.

Abstract: Some implementations described herein include systems and techniques for fabricating a multi-dimension through silicon via structure in a three-dimensional integrated circuit device. The multi-dimension through silicon via structure includes a first columnar structure having a first width and a second columnar structure including a second width that is greater relative to the first width. The first columnar structure may include a low electrical capacitance and be configured for electrical signaling within the three-dimensional integrated circuit device. The second columnar structure may be configured to provide power to integrated circuitry of the three-dimensional integrated circuit device and also be configured to conduct heat through the three-dimensional integrated circuit device for thermal management of the three-dimensional integrated circuit device. Additionally, a pattern including the second columnar structure may be used for alignment purposes.

Abstract: An integrated circuit (IC) device includes a substrate. The IC device includes a multi-layer interconnect structure disposed over a first side of the substrate. The multi-layer interconnect structure includes a plurality of metal layers. The IC device includes a first portion of a through-substrate via (TSV) disposed over the first side of the substrate. The first portion of the TSV includes a plurality of conductive components belonging to the plurality of metal layers of the multi-layer interconnect structure. The IC device includes a second portion of the TSV that extends vertically through the substrate from the first side to a second side opposite the first side. The second portion of the TSV is electrically coupled to the first portion of the TSV.

Abstract: A device and method for generating article markup information are provided. The method for generating article markup information includes the following. Segmentation processing is performed on an article to generate a segmentation result. Name entity recognition is performed on the segmentation result to generate a first recognition result. Whether the segmentation result includes any word in an expansion list is determined. Expanded entity classification conversion is performed on the first recognition result to generate a second recognition result. The second recognition result and the segmentation result are used as markup information.

Abstract: A road structure reconstructed from large-scale independent underground garage and a construction method, which solves the problem of a newly constructed urban expressway passing through large underground space. The technical point is a construction method for the road structure reconstructed from large-scale independent underground garage, including the following steps: S100: segmentation for the garage, S200: preparation before construction: the materials and equipment required for construction are transported to the site, and the construction site is cleaned, S300: reconstruction for the front section, S400: reconstruction for the middle section, S500: reconstruction for the rear section. The inventiveness of the present disclosure is the application of segmentation construction, the front section is completely obsoleted, a transition section is provided at the middle, and the design of the rear section adopts a double-deck road, thus the original underground garage structure is fully utilized.

Abstract: A method of generating an IC layout diagram includes receiving the IC layout diagram including an active region, a gate region extending across the active region from a first active region edge to a second active region edge, and a gate via positioned at a location along the gate region between the first and second edges, configuring a delta resistance network including the first and second edges, a midpoint between the first and second edges, and resistance values based on the location and first and second edges, and performing a simulation based on the delta resistance network.

Abstract: A method for processing a plurality of queries is provided according to embodiments of the present disclosure. In this method, based on a plurality of queries and an execution plan for the plurality of quires, a plurality of record identification (ID) numbers can be stored into a pool in a numerical order. Each of the plurality of record ID numbers can identify a data record in a database. Then, the execution plan can be performed to batch a plurality of data records corresponding to the plurality of record ID numbers in the database based on a distribution of the plurality of record ID numbers in the pool.

Abstract: A package device can include: a package body having a support body and an encapsulating body configured to encapsulate a conductive body of the package device; at least one extraction electrode electrically connected to the conductive body, and having a part exposed outside the package body; and where the support body is located on only part of a bottom surface of the encapsulating body, and protrudes from the bottom surface of the encapsulating body to form a cavity defined by the remaining exposed bottom surface of the encapsulating body and inner side surface of the supporting body.

Abstract: A semiconductor structure includes a substrate, a channel region, a gate structure, and source/drain regions. The channel region is over the substrate. The gate structure is over the channel region, and includes a high-k dielectric layer, a tungsten layer over the high-k dielectric layer, and a fluorine-containing work function layer over the tungsten layer. The source/drain regions are at opposite sides of the channel region.

Abstract: An apparatus can include memory devices and a memory controller coupled to the memory devices via memory channels. The memory channels can disable a first memory channel associated with a first memory die in a respective memory chip of a memory device and perform a memory operation via a second memory channel involving a second memory die in the respective memory chip.

Abstract: Disclosed are a super-resolution imaging system (1, 41, 51), a super-resolution imaging method, a biological sample identification system (4, 61) and method, a nucleic acid sequencing imaging system (5) and method, and a nucleic acid identification system (6) and method. The super-resolution imaging system (1, 41, 51) includes an illumination system (A) and an imaging system (B). The illumination system (A) outputs excitation light to irradiate a biological sample to generate excited light, and the imaging system (B) collects and records the excited light to generate an excited light image. The illumination system (A) includes an excitation light source (10, 10a) and a structured light generation and modulation device (11, 11a). The excitation light source (10, 10a) outputs the excitation light, and the structured light generation and modulation device (11, 11a) modulates the excitation light into structured light to irradiate the biological sample to generate the excited light.

Abstract: The present invention relates to a polybutylene terephthalate composition, and an article derived from the polybutylene terephthalate composition comprising as component (A) polybutylene terephthalate (PBT) resin, as component (B) vinyl aromatic-based polymer comprising units which are derived from vinyl aromatic monomers, and as component (C) reinforcement agent.

Abstract: The present invention relates to a polybutylene terephthalate composition, comprising (A) 45 to 75% by weight of polybutylene terephthalate, (B) 20 to 45% by weight of at least one carbon fiber, (C) 0 to 20% by weight of at least one solid filler other than the carbon fiber (B), and (D) 0 to 30% by weight of at least one thermoplastic polyester other than polybutylene terephthalate, each being based on the total weight of the polybutylene terephthalate composition, wherein the at least one carbon fiber has a carbon content of 93% by weight or greater, and comprises a sizing agent other than epoxy sizing agent. The present invention also relates to an EMI shielding article produced from the polybutylene terephthalate composition.

Abstract: A method of generating an IC layout diagram includes receiving a first gate resistance value of a gate region in an IC layout diagram, the first gate resistance value corresponding to a location of a gate via positioned within an active region and along a width of the gate region extending across the active region, determining a second gate resistance value based on the location and the width, using the first and second resistance values to determine that the IC layout diagram does not comply with a design specification, and based on the non-compliance with the design specification, modifying the IC layout diagram.

Abstract: A substrate has a first side and a second side opposite the first side. A first transistor has a first gate, a second transistor has a second gate, and a third transistor has a third gate. The first gate, the second gate, and the third gate are each disposed over the first side of the substrate. The second gate is disposed between the first gate and the third gate. The first gate and the third gate have different material compositions. A structure is disposed over the second side of the substrate. The structure includes a first opening aligned with the first transistor, a second opening aligned with the second transistor, and a third opening aligned with the third transistor. A sensing film is disposed over the second side of the substrate. The sensing film is configured to attach to one or more predefined miniature targets.

Abstract: A substrate has a first side and a second side vertically opposite to the first side. A sensing transistor is disposed at least in part over the first side of the substrate. A plurality of voltage reference transistors is disposed at least in part over the first side of the substrate. The voltage reference transistors are disposed on different lateral sides of the sensing transistor. A structure is disposed over the second side of the substrate. The structure defines one or more openings configured to collect a fluid. A sensing film is disposed over the second side of the substrate, wherein the sensing transistor is configured to detect, at least in part through capacitive coupling, a presence of one or more predefined miniature targets in the fluid that attach to the sensing film in the opening that is vertically aligned with the sensing transistor.

Abstract: An interconnect structure is disposed over a semiconductor substrate. The interconnect structure includes a plurality of interconnect layers. A first thin-film transistor (TFT) and a second TFT disposed over the semiconductor substrate. The first TFT and the second TFT each vertically extend through at least a subset of the interconnect layers. An opening is formed in the interconnect structure. The opening is disposed between the first TFT and the second TFT. A sensing film is disposed over a bottom surface and side surfaces of the opening.

Abstract: The invention discloses a polybutylene terephthalate composition comprising as component (A) polybutylene terephthalate resin in an amount of from 40 wt % to 90 wt %, as component (B) glass fiber having low dielectric constant and dissipation factor measured according to GB 9534-88 in an amount of 10 wt % to 60 wt %. The invention also disclosed a radar device component containing the polybutylene terephthalate composition.

Abstract: A semiconductor structure includes a sensor, a patterned dielectric layer, and a cover disposed on the patterned dielectric layer. The sensor includes a bio-sensing device and at least one voltage-reference device disposed in proximity to the bio-sensing device. The bio-sensing device includes a first field effect transistor (FET) and a first sensing portion of a sensing film capacitively coupled to the first FET, and the first sensing portion is concave toward the first FET. The at least one voltage-reference device includes a second FET and a second sensing portion of the sensing film capacitively coupled to the second FET. The patterned dielectric layer is disposed on the sensing film and includes at least one sensing well located above the at least one voltage-reference device and the bio-sensing device. The cover includes fluid channels communicating with the at least one sensing wells.