Abstract: An embodiment is a device including a first die and a substrate including a first surface and a second surface opposite the first surface. The device also includes an active device on the first surface of the substrate. The device also includes a first interconnect structure on the first surface of the substrate. The device also includes a through substrate via extending through the first interconnect structure and the substrate to the second surface of the substrate, the through substrate via being electrically coupled to metallization patterns in the first interconnect structure. The device also includes one or more material-filled trench structures extending from the second surface of the substrate into the substrate, the one or more material-filled trench structures being electrically isolated from the through substrate via.

Abstract: A method includes forming first nanostructures over a first region of a substrate; forming second nanostructures over a second region of the substrate; forming first gate structures around the first nanostructures; replacing the second nanostructures with isolation regions; and forming a seal ring over the substrate, wherein the seal ring is between the first region and the second region.

Abstract: A cooling system includes a control device, a chiller unit, a cooling tower, and an ice water storage tank. The chiller unit, the ice water storage tank, and the data center are coupled through a pipeline. According to a first condition, the chiller unit provides cooling water to the data center. According to a second condition, the chiller unit provides cooling water to the data center and the ice water storage tank. According to a third condition, the ice water storage tank provides cooling water to the data center and the chiller unit refills cooling water to the ice water storage tank, and heated water of the data center flows to the chiller unit.

Abstract: Methods, systems, and devices for determining priority of transport channels and transmission signals. Some embodiments can be used in wireless communication embodiments in which multiple uplink transport channels or transmission signals need to be concurrent transmitted, such as in dual-connectivity mode, where the determined priority can be used to preferentially allocate uplink transmit power to higher priority transport channels and transmission signals.

Abstract: A method includes forming a device die including forming integrated circuits on a semiconductor substrate; and forming a thermally conductive pillar extending into the semiconductor substrate. A cooling medium is attached over and contacting the semiconductor substrate to form a package, wherein the cooling medium is thermally coupled to the thermally conductive pillar.

Abstract: Interconnect structures for front-to-front stacked chips/dies and methods of fabrication thereof are disclosed herein. An exemplary system on integrated circuit (SoIC) includes a first die that is front-to-front bonded with a second die, for example, by bonding a first topmost metallization layer of a first frontside multilayer interconnect of the first die to a second topmost metallization layer of a second frontside multilayer interconnect of the second die. A through via extends partially through the first frontside multilayer interconnect of the first die, through a device layer of the first die, through a backside power rail of the first die, and through a carrier substrate. The backside power rail is between the carrier substrate and the device layer, and the backside power rail may be a portion of a backside multilayer interconnect of the first die. The through via may be connected to a redistribution layer (RDL) structure.

Abstract: A method includes receiving a workpiece including a device layer disposed on a frontside of the workpiece, forming a frontside interconnect structure over the device layer, attaching a carrier substrate over the frontside interconnect structure, and etching from a backside of the workpiece to form first trenches and second trenches. The first trenches extend partially into the carrier substrate for a distance less than the second trenches. The method also includes forming a plurality of first conductive features in the first trenches and a plurality of second conductive features in the second trenches, forming a backside interconnect structure covering the first conductive features and the second conductive features, and thinning the carrier substrate from the frontside of the workpiece to expose the second conductive features. The first conductive features remain partially embedded in the carrier substrate.

Abstract: A method includes forming a first multilayer interconnect structure over a first side of a device layer, forming a first portion of a second multilayer interconnect structure under a second side of the device layer, forming a trench that extends through the second dielectric layer, the device layer, and the first dielectric layer, forming a conductive structure in the trench, and forming a second portion of the second multilayer interconnect structure under the first portion of the second multilayer interconnect structure. The second portion of the second multilayer interconnect structure includes patterned metal layers disposed in a third dielectric layer, and wherein one or more of the patterned metal layers are in electrical connection with the conductive structure.

Abstract: An approach is provided in which a method, system, and program product analyze, while training a machine learning model, a set of first data transformation operators in a first data preparation pipeline that generates a plurality of constructed features from a set of training data. The method, system, and program product create a plurality of second data preparation pipelines from the first data preparation pipeline, wherein the set of first data transformation operators are converted to a set of second data transformation operators and each assigned to one of the plurality of second data preparation pipelines. The method, system, and program product deploy the plurality of second data preparation pipelines to a runtime system.

Abstract: A temperature control device includes a temperature sensor configured to detect a temperature within a server. When the temperature in the server is below a preset temperature, the control unit controls an interior heating assembly to heat the server, and closes a ventilation assembly to retain heat within the server. When the temperature in the server has reached the preset temperature, the control unit controls the heating assembly to stop the internal heating, and controls the ventilation assembly to open, to allow dissipation of the heat from the server.

Abstract: The present disclosure relates to a data writing method and apparatus of a NAND flash, and a storage medium. The method includes: for each channel in the NAND flash, pairing all logic units, namely LUNs, in the channel so that each LUN pair includes at least two LUNs; and for each LUN pair, sequentially writing data to one same page in a plurality of pages corresponding to a program mode included in each word line of each LUN in the LUN pair, and after completing data writing to the same page of the word line of all the LUNs in the LUN pair, sequentially writing data to a next same page in the plurality of pages of the word line of each LUN in the LUN pair, until the data writing is sequentially performed on a last same page in the plurality of pages of the word line of each LUN in the LUN pair. Therefore, the transmission efficiency of a NAND bus can be improved, and the data writing performance of the NAND flash can be improved.

Abstract: A method of generating an IC layout diagram includes receiving the IC layout diagram including an active region, a gate region extending across the active region from a first active region edge to a second active region edge, and a gate via positioned at a location along the gate region between the first and second active region edges, calculating a gate resistance value based on the location and first and second active region edges, based on the resistance value, modifying the IC layout diagram by changing the location of the gate via along the gate region and/or adding another gate via positioned at another location along the gate region, and storing the modified IC layout diagram in a storage device.

Abstract: Various embodiments of the present application are directed towards an ion-sensitive field-effect transistor for enhanced sensitivity. In some embodiments, a substrate comprises a pair of first source/drain regions and a pair of second source/drain regions. Further, a first gate electrode and a second gate electrode underlie the substrate. The first gate electrode is laterally between the first source/drain regions, and the second gate electrode is laterally between the second source/drain regions. An interconnect structure underlies the substrate and defines conductive paths electrically shorting the second source/drain regions and the second gate electrode together. A passivation layer is over the substrate and defines a first well and a second well. The first and second wells respectively overlie the first and second gate electrodes, and a sensing layer lines the substrate in the first and second wells. In some embodiments, sensing probes are in the first well, but not the second well.

Abstract: A one-shot neural architecture search method referred to as MergeNAS by merging different types of convolutions into a single operation. This mergence approach reduces the search cost to roughly half a GPU-day as well as alleviates the over-fitting problem caused by a traditional differentiable architecture search (DARTS) approach by reducing the number of redundant parameters.

Abstract: A method of generating an IC layout diagram includes receiving the IC layout diagram including an active region, a gate region extending across the active region from a first active region edge to a second active region edge, and a gate via positioned at a location along the gate region between the first and second edges, configuring a delta resistance network including the first and second edges, a midpoint between the first and second edges, and resistance values based on the location and first and second edges, and performing a simulation based on the delta resistance network.

Abstract: The present invention relates to a polybutylene terephthalate composition, comprising as component (A) polybutylene terephthalate (PBT) resin, as component (B) polyester copolymer with melting point from 105° C. to 185° C., as component (C) vinyl-based polymer, and optionally as component (D) glass bubbles. The present invention also relates to a composite of plastic/metal hybrid, which comprises metal article and the polybutylene terephthalate composition of the present invention which is joined to and integrated with the metal article.

Abstract: A detection element of biological subcutaneous features and a wearable device thereof are provided. The element for detecting biological subcutaneous features has a substrate, a light-detecting semiconductor chip, a grid structure, and a cover. The light-detecting semiconductor chip is located on the substrate for detecting red light or near-infrared light signals. The grid structure including a plurality of opaque light-absorbing blocking walls is located on the light-detecting semiconductor chip for blocking side light and increasing the proportion of near-vertical incident light. The cover is located on the grid structure and serves as a protection lid. The wearable device for detecting biological subcutaneous features has more than one light source of red light or near-infrared light and a plurality of detection elements. The arrangement of the opaque light-absorbing blocking walls that are parallel to each other are substantially parallel to the light-emitting directions of the light source.

Abstract: The present invention relates to a polybutylene terephthalate composition, comprising (A) 40 to 99.8% by weight of polybutylene terephthalate, (B) 0.2 to 10% by weight of at least one conductive filler selected from the group consisting of carbon nanotubes, carbon nanostructures, and a combination thereof, and (C) 0 to 50% by weight of glass fiber, each being based on the total weight of the poly butylene terephthalate composition, wherein the carbon nanostructures each comprise a plurality of carbon nanotubes which are branched, crosslinked, and/or sharing common walls with one another. The present invention also relates to an EMI shielding article produced from the polybutylene terephthalate composition.

Abstract: An immersion cooling tank includes a tank body and a liquid flow tube. The tank body holds a coolant and an electronic device. The tank body defines an inlet and an outlet. The inlet and the outlet are respectively located at opposite ends of the electronic device for inputting and outputting the coolant. The coolant flows through the electronic device. The liquid flow tube includes at least one adjuster. The liquid flow tube is located inside the tank body and coupled to at least one of the inlet or the outlet. The at least one adjuster faces the electronic device for controlling an amount of the coolant flowing in or out of the tank body.

Abstract: A wall mountable sensor module includes a housing defining an internal space that is segmented into a first internal space and a second internal space. The first internal space defines an air channel that extends from an air inlet to an air outlet. Two or more sensors are configured to be exposed to the air flow channel. A first sensor is configured to detect a first air parameter and a second sensor is configured to detect a second different air parameter, wherein the second sensor is situated downstream of the first sensor in the air flow channel. The sensor module includes a fan housed by the housing, the fan configured to cause an airflow to flow in through the air inlet, through the air flow channel thereby exposing each of the sensors to the airflow, and out through the air outlet.