Patents by Inventor Ke-Wei Tung

Ke-Wei Tung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6808991
    Abstract: Roughly described, therefore, in accordance with a preferred embodiment of the present invention, a method is provided for fabricating an N-bit memory device with self-aligned buried diffuision implants and two isolated ONO segments in one cell. The method includes the steps of forming an ONO layer on a substrate, depositing a polysilicon layer, patterning the polysilicon layer, implanting barrier diffusion, trimming the photoresist layer on the polysilicon layer, etching the polysilicon layer by using the trimmed photoresist layer as mask, then removing the photoresist. After removing the photoresist, a nitride layer is filled in the patterned polysilicon layer openings. The etching steps are preformed by using the nitride layer as a mask. The polysilicon layer and part of the ONO layer are removed, and the gate oxide layer is exposed. Two isolated ONO segments are formed by these etching steps. A polysilicon gate is then formed on the gate oxide layer.
    Type: Grant
    Filed: November 19, 2003
    Date of Patent: October 26, 2004
    Assignee: Macronix International Co., Ltd.
    Inventor: Ke-Wei Tung
  • Publication number: 20040173317
    Abstract: A system for removing photoresist and providing in-situ discharge. A resist stripper system includes a vertical downstream chamber, a gas passageway at the top of the vertical downstream chamber to supply an inert gas, and a wafer plate at the bottom inside the vertical downstream chamber to support and fix a wafer. A plasma generating system on the vertical downstream chamber near the gas passageway induces plasma of an inert gas. A first gas outlet on the vertical downstream chamber between the wafer plate and the plasma generating system exhausts the plasma, and a second gas outlet on the vertical downstream chamber beneath the wafer plate exhausts resist residue. A power supply is connected to the wafer plate to apply a positive bias to the wafer to attract electrons.
    Type: Application
    Filed: March 7, 2003
    Publication date: September 9, 2004
    Inventor: Ke-Wei Tung
  • Patent number: 6442950
    Abstract: A cooling system of chamber with a removable liner includes follows gas temperature adjusting assembly, gas supplying assembly, and gas controlling assembly. Gas temperature adjusting assembly is located between removable liner and a wall of said chamber. Gas supplying assembly is connected with gas temperature adjusting assembly and could be used to supply a gas which is required by gas temperature adjusting assembly. Gas controlling assembly is connected with gas supplying assembly and could be used to control both flow rate and flow account of gas, such that temperature could be adjusted right now.
    Type: Grant
    Filed: May 23, 2001
    Date of Patent: September 3, 2002
    Assignee: Macronix International Co., Ltd.
    Inventor: Ke-Wei Tung