Abstract: An electrostatic discharge protection device having a P-type substrate, a common N-well formed in the P-type substrate, a common N-doped region formed in the first common N-well, wherein the common N-doped region is electrically connected to a reference voltage node. The device further has a common P-doped region formed in the common N-well, wherein the common P-doped region surrounds the common N-doped region, the common P-doped region and the common N-well form a common diode, a plurality of peripheral N-wells formed in the P-type substrate and surrounding the common N-well, each of the peripheral N-wells comprising a P-type doped region and a N-type doped region, wherein the P-type doped region is electrically connected to one of a plurality of I/O terminals, and a circular P-doped region formed in the P-type substrate and disposed between the common N-well and the peripheral N-wells, and the circular P-doped region surrounding the common N-well.

Abstract: An electrostatic discharge protection device having a P-type substrate, a common N-well formed in the P-type substrate, a common N-doped region formed in the first common N-well, wherein the common N-doped region is electrically connected to a reference voltage node. The device further has a common P-doped region formed in the common N-well, wherein the common P-doped region surrounds the common N-doped region, the common P-doped region and the common N-well form a common diode, a plurality of peripheral N-wells formed in the P-type substrate and surrounding the common N-well, each of the peripheral N-wells comprising a P-type doped region and a N-type doped region, wherein the P-type doped region is electrically connected to one of a plurality of I/O terminals, and a circular P-doped region formed in the P-type substrate and disposed between the common N-well and the peripheral N-wells, and the circular P-doped region surrounding the common N-well.

Abstract: An electrostatic discharge protection device, having a P-type semiconductor substrate set as floating; a first N-well and a second N-well formed in the P-type substrate; a first P-doped region and a second P-doped region formed in the first N-well and the second N-well, respectively. The first N-well and the first P-doped region form a first diode, and the second N-well and the second P-doped region form a second diode. A first N-doped region and a second N-doped region formed in the first N-well and the second N-well respectively. A third P-doped region is formed in the P-type substrate, wherein the third P-doped region is disposed between the first N-well and the second N-well, and the third P-doped region is electrically connected to the first N-doped region and the second P-doped region.

Abstract: An integrated circuit and a protection circuit capable of protecting electrostatic discharge (ESD) damage. The integrated circuit comprises a first pad, a ground pad, a second pad, a device circuitry, a discharging unit, and a discharging controller. The discharging unit comprises first and second transistors in series. The discharging controller comprises an ESD connection unit, and a voltage clamping unit. The ESD connection unit, coupled to the first pad and the discharging unit, receives an ESD pulse to establish a first control voltage to turn on the first transistor in the ESD event. The voltage clamping unit, coupled to the ESD connection unit and the first, second and ground pads, clamps the ESD pulse to establish a second control voltage to turn on the second transistor in the ESD event, and receives an operation voltage at the first pad to turn off the second transistor in normal operation.

Abstract: An integrated circuit and a protection circuit capable of protecting electrostatic discharge (ESD) damage. The integrated circuit comprises a first pad, a ground pad, a second pad, a device circuitry, a discharging unit, and a discharging controller. The discharging unit comprises first and second transistors in series. The discharging controller comprises an ESD connection unit, and a voltage clamping unit. The ESD connection unit, coupled to the first pad and the discharging unit, receives an ESD pulse to establish a first control voltage to turn on the first transistor in the ESD event. The voltage clamping unit, coupled to the ESD connection unit and the first, second and ground pads, clamps the ESD pulse to establish a second control voltage to turn on the second transistor in the ESD event, and receives an operation voltage at the first pad to turn off the second transistor in normal operation.

Abstract: An electro-static discharge, ESD, protection circuit is disclosed. While protecting an ESD event between a given pad and a ground pad, the ESD protection circuit triggers a clamp for ESD protection according to a voltage difference between the given pad and a power pad. Generally, chips already have capacitance between the power pads and the ground pads, such as capacitance contributed by decoupling capacitors for power regulation. Therefore, when the ESD event happens between the given pad and the ground pad, voltage of the power pad holds to make a voltage difference enough for triggering the clamp. Accordingly, the ESD protection circuit can reduce layout area by taking advantage of the original capacitance of chips.

Abstract: An electro-static discharge, ESD, protection circuit is disclosed. While protecting an ESD event between a given pad and a ground pad, the ESD protection circuit triggers a clamp for ESD protection according to a voltage difference between the given pad and a power pad. Generally, chips already have capacitance between the power pads and the ground pads, such as capacitance contributed by decoupling capacitors for power regulation. Therefore, when the ESD event happens between the given pad and the ground pad, voltage of the power pad holds to make a voltage difference enough for triggering the clamp. Accordingly, the ESD protection circuit can reduce layout area by taking advantage of the original capacitance of chips.

Abstract: This invention discloses a semiconductor device with latch-up prevention mechanisms. According to one embodiment, it comprises a first N-type region, wherein one or more P-type metal-oxide-semiconductor (PMOS) devices are disposed therein, a second N-type region adjacent to the first N-type region, wherein one or more PMOS devices are also disposed therein, and a P-type region disposed between the first and second N-type regions, wherein one or more guard ring is disposed therein, so that the semiconductor device is more immune to latch-up.

Abstract: This invention discloses a semiconductor device with latch-up prevention mechanisms. According to one embodiment, it comprises a first doping region, wherein one or more semiconductor devices are disposed therein and coupling to a first supply voltage, a second doping region adjacent to the first doping region, wherein the second doping region is an Nwell, and at least one PMOS capacitor is disposed therein and coupled to a second supply voltage higher than the first supply voltage, wherein one or more deep N-type implant regions are disposed beneath a bulk pick-up N+ region of the PMOS device in the second doping region, and a P-type region disposed between the first and second doping regions.

Abstract: This invention discloses a semiconductor device with latch-up prevention mechanisms. According to one embodiment, it comprises a first N-type region, wherein one or more P-type metal-oxide-semiconductor (PMOS) devices are disposed therein, a second N-type region adjacent to the first N-type region, wherein one or more PMOS devices are also disposed therein, and a P-type region disposed between the first and second N-type regions, wherein one or more guard rings are disposed therein, so that the semiconductor device is more immune to latch-up.