Abstract: A scheduling method performed by a computing device that includes a plurality of processors, a type of at least one instruction set of instruction sets supported by at least one of the plurality of processors is different from a type of an instruction set of instruction sets supported by another processor, where the scheduling method includes obtaining a type of an instruction set of an application, selecting a target processor from the plurality of processors, where the type of the instruction set of the application is a subset of types of a plurality of instruction sets of instruction sets supported by the target processor, and allocating the application to the target processor for execution.

Abstract: Embodiments described herein provide an apparatus comprising a processor to reserve a block of physical memory communicatively coupled to a processor, allocate a first portion of the block of physical memory for use with one or more processes executing on the processor, the first portion configured as a single memory page having a first page size, and in response to a determination that an amount of physical memory required by the one or more processes executing on the processor exceeds a first threshold allocate additional memory to the first portion of the block of physical memory, and increase the single memory page from a first page size to a second page size. Other embodiments may be described and claimed.

Abstract: Embodiments described herein provide an apparatus comprising a processor to reserve a block of physical memory communicatively coupled to a processor, allocate a first portion of the block of physical memory for use with one or more processes executing on the processor, the first portion configured as a single memory page having a first page size, and in response to a determination that an amount of physical memory required by the one or more processes executing on the processor exceeds a first threshold allocate additional memory to the first portion of the block of physical memory, and increase the single memory page from a first page size to a second page size. Other embodiments may be described and claimed.

Abstract: Disclosed are a method and device for determining a warehouse inventory, which relate to the technical field of computers. One implementation mode of the method comprises: determining, based on a corresponding relationship between virtual storage spaces and containers in a warehouse, the containers located in the virtual storage spaces; acquiring, in accordance with a corresponding relationship between containers, items, and item quantities, the item quantities of the items located in the containers, thereby obtaining a total quantity of the items in the virtual storage spaces; and acquiring the quantities of the items located in physical storage spaces in the warehouse, and updating a total inventory in the warehouse by combining the quantities of the items located in the physical storage spaces with the total quantity of the items in the virtual storage spaces.

Abstract: Embodiments described herein provide an apparatus comprising a processor to reserve a block of physical memory communicatively coupled to a processor, allocate a first portion of the block of physical memory for use with one or more processes executing on the processor, the first portion configured as a single memory page having a first page size, and in response to a determination that an amount of physical memory required by the one or more processes executing on the processor exceeds a first threshold allocate additional memory to the first portion of the block of physical memory, and increase the single memory page from a first page size to a second page size. Other embodiments may be described and claimed.

Abstract: In an embodiment, a first portion of a cache memory is associated with a first core. This first cache memory portion is of a distributed cache memory, and may be dynamically controlled to be one of a private cache memory for the first core and a shared cache memory shared by a plurality of cores (including the first core) according to an addressing mode, which itself is dynamically controllable. Other embodiments are described and claimed.

Abstract: A processor includes a first core including a first cache including a cache line, a second core including a second cache, and a cache controller to set a flag stored in a flag section of the cache line of the first cache to one of a processor share (PS) state in response to data stored in the cache line being shared by the second cache, or to a global share (GS) state in response to the data stored in the first cache line being shared by a third cache of a second processor.

Abstract: Techniques are described to generate an index for a texture. The index can be used to retrieve a portion of one or more textures from a cache. The index can be adapted based on static texture attributes or direction attributes in order to attempt to achieve texture cache efficiency. Static texture attributes can include, bit are not limited to, 1-dimensional texture, 2-dimensional texture, 3-dimensional texture, or MIPmaps texture, original memory address. Direction attributes can be, but are not limited to, u-major or v-major directions.

Abstract: A processor includes an execution unit and a filter module. The filter module includes logic to receive an instruction, determine whether the instruction was previously executed to prefetch information from a cache, and discard the instruction based on a determination that the instruction was previously executed to prefetch the information from the cache.

Abstract: Techniques are described to configure a cache line structure based on attributes of a draw call and access direction of a texture. Attributes of textures (e.g., texture format and filter type), samplers, and shaders used by the draw call can be considered to determine the line size of a cache. Access direction can be considered to reduce the number of lines that are used to store texels required by a sample request.

Abstract: In an embodiment, a first portion of a cache memory is associated with a first core. This first cache memory portion is of a distributed cache memory, and may be dynamically controlled to be one of a private cache memory for the first core and a shared cache memory shared by a plurality of cores (including the first core) according to an addressing mode, which itself is dynamically controllable. Other embodiments are described and claimed.

Abstract: Techniques are described to configure a cache line structure based on attributes of a draw call and access direction of a texture. Attributes of textures (e.g., texture format and filter type), samplers, and shaders used by the draw call can be considered to determine the line size of a cache. Access direction can be considered to reduce the number of lines that are used to store texels required by a sample request.

Abstract: Techniques are described to generate an index for a texture. The index can be used to retrieve a portion of one or more textures from a cache. The index can be adapted based on static texture attributes or direction attributes in order to attempt to achieve texture cache efficiency. Static texture attributes can include, bit are not limited to, 1-dimensional texture, 2-dimensional texture, 3-dimensional texture, or MIPmaps texture, original memory address. Direction attributes can be, but are not limited to, u-major or v-major directions.