Abstract: An example device includes a first interface configured to couple to a first memory that is configured to store an image that includes a set of slices; a second interface configured to couple to a second memory; and a direct memory access circuit coupled to the first and second interfaces. The direct memory access circuit receives a transaction that specifies a read of a slice of the set of slices; and based on the transaction, reads the slice from the first memory; performs operations to the slice; and stores the slice in the second memory.

Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement thread scheduling for multithreaded data processing environments are disclosed. Example thread schedulers disclosed herein for a data processing system include a buffer manager to determine availability of respective buffers to be acquired for respective processing threads implementing respective functional nodes of a processing flow, and to identify first ones of the processing threads as stalled due to unavailability of at least one buffer in the respective buffers to be acquired for the first ones of the processing threads. Disclosed example thread schedulers also include a thread execution manager to initiate execution of second ones of the processing threads that are not identified as stalled.

Abstract: An example apparatus includes: a first interface configured to couple to a processor core; a second interface configured to couple to a first memory configured to store an image that includes a set of slices; a third interface coupled to the first interface, the third interface configured to couple to a second memory; a direct memory access circuit coupled to the second interface and the third interface and configured to: receive a transaction from the second interface, wherein the transaction specifies a read of a slice of the set of slices; and based on the transaction: read the slice from the first memory; perform on-the-fly operations to the slice; and store the slice in the second memory.

Abstract: Various embodiments disclosed herein relate to compute offloading by supplying operands to hardware accelerators from central processing units. An example embodiment includes a system configured to perform compute offloading. The system comprises a processing unit configured to write data to a memory and a memory adaptor bridge coupled between the processing unit and the memory. The memory adaptor bridge is configured to, in response to an attempt by the processing unit to write an operand to a memory location mapped to a function of a hardware accelerator, write the operand to a different memory location accessible by the hardware accelerator. The memory adaptor bridge is further configured to obtain a result of the function performed on the operand by the hardware accelerator and provide the result of the function to a memory location accessible by the processing unit.

Abstract: In an example, a method includes storing code for a first central processing unit (CPU) executing a first application in a first region of a memory, and storing code for a second CPU executing a second application in a second region of the memory. The method includes storing shared code for the first CPU and the second CPU in a third region of the memory. The method includes storing read-write data for the first CPU in a fourth region of the memory and storing read-write data for the second CPU in a fifth region of the memory. The method includes translating a first address from a first unique address space for the first CPU to a shared address space in the third region, and translating a second address from a second unique address space for the second CPU to the shared address space in the third region.

Abstract: An example apparatus includes: a first interface configured to couple to a processor core; a second interface configured to couple to a first memory configured to store an image that includes a set of slices; a third interface coupled to the first interface, the third interface configured to couple to a second memory; a direct memory access circuit coupled to the second interface and the third interface and configured to: receive a transaction from the second interface, wherein the transaction specifies a read of a slice of the set of slices; and based on the transaction: read the slice from the first memory; perform on-the-fly operations to the slice; and store the slice in the second memory.

Abstract: Method and system to improve the performance of a video encoder. The method includes processing an initial video signal in a front-end image pre-processor to obtain a processed video signal and processor information respecting the signal, providing the processed video signal and the processor information to a video encoder, and encoding the video signal in the video encoder according to the processor information to provide an encoded video signal for storage. The system includes a video pre-processor connectable to receive an initial video signal. The video encoder in communication with the video pre-processor receives a processed video signal and a processor information. A storage medium in communication with the video encoder stores an encoded video signal.

Abstract: Methods, apparatus, systems and articles of manufacture for an example event processor are disclosed to retrieve an input event and an input event timestamp corresponding to the input event, generate an output event based on the input event and the input event timestamp, in response to determination that an input event threshold is exceeded within a threshold of time, and an anomaly detector to retrieve the output event, determine whether the output event indicates threat to functional safety of a system on a chip, and in response to determining the output event indicates threat to functional safety of the system on a chip, adapt a process for the system on a chip to preserve functional safety.

Abstract: Method and system to improve the performance of a video encoder. The method includes processing an initial video signal in a front-end image pre-processor to obtain a processed video signal and processor information respecting the signal, providing the processed video signal and the processor information to a video encoder, and encoding the video signal in the video encoder according to the processor information to provide an encoded video signal for storage. The system includes a video pre-processor connectable to receive an initial video signal. The video encoder in communication with the video pre-processor receives a processed video signal and a processor information. A storage medium in communication with the video encoder stores an encoded video signal.

Abstract: Method and system to improve the performance of a video encoder. The method includes processing an initial video signal in a front-end image pre-processor to obtain a processed video signal and processor information respecting the signal, providing the processed video signal and the processor information to a video encoder, and encoding the video signal in the video encoder according to the processor information to provide an encoded video signal for storage. The system includes a video pre-processor connectable to receive an initial video signal. The video encoder in communication with the video pre-processor receives a processed video signal and a processor information. A storage medium in communication with the video encoder stores an encoded video signal.

Abstract: Methods, apparatus, systems and articles of manufacture for an example event processor are disclosed to retrieve an input event and an input event timestamp corresponding to the input event, generate an output event based on the input event and the input event timestamp, in response to determination that an input event threshold is exceeded within a threshold of time, and an anomaly detector to retrieve the output event, determine whether the output event indicates threat to functional safety of a system on a chip, and in response to determining the output event indicates threat to functional safety of the system on a chip, adapt a process for the system on a chip to preserve functional safety.

Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement thread scheduling for multithreaded data processing environments are disclosed. Example thread schedulers disclosed herein for a data processing system include a buffer manager to determine availability of respective buffers to be acquired for respective processing threads implementing respective functional nodes of a processing flow, and to identify first ones of the processing threads as stalled due to unavailability of at least one buffer in the respective buffers to be acquired for the first ones of the processing threads. Disclosed example thread schedulers also include a thread execution manager to initiate execution of second ones of the processing threads that are not identified as stalled.

Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement thread scheduling for multithreaded data processing environments are disclosed. Example thread schedulers disclosed herein for a data processing system include a buffer manager to determine availability of respective buffers to be acquired for respective processing threads implementing respective functional nodes of a processing flow, and to identify first ones of the processing threads as stalled due to unavailability of at least one buffer in the respective buffers to be acquired for the first ones of the processing threads. Disclosed example thread schedulers also include a thread execution manager to initiate execution of second ones of the processing threads that are not identified as stalled.

Abstract: Method and system to improve the performance of a video encoder. The method includes processing an initial video signal in a front-end image pre-processor to obtain a processed video signal and processor information respecting the signal, providing the processed video signal and the processor information to a video encoder, and encoding the video signal in the video encoder according to the processor information to provide an encoded video signal for storage. The system includes a video pre-processor connectable to receive an initial video signal. The video encoder in communication with the video pre-processor receives a processed video signal and a processor information. A storage medium in communication with the video encoder stores an encoded video signal.

Abstract: Method and system to improve the performance of a video encoder. The method includes processing an initial video signal in a front-end image pre-processor to obtain a processed video signal and processor information respecting the signal, providing the processed video signal and the processor information to a video encoder, and encoding the video signal in the video encoder according to the processor information to provide an encoded video signal for storage. The system includes a video pre-processor connectable to receive an initial video signal. The video encoder in communication with the video pre-processor receives a processed video signal and a processor information. A storage medium in communication with the video encoder stores an encoded video signal.

Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement thread scheduling for multithreaded data processing environments are disclosed. Example thread schedulers disclosed herein for a data processing system include a buffer manager to determine availability of respective buffers to be acquired for respective processing threads implementing respective functional nodes of a processing flow, and to identify first ones of the processing threads as stalled due to unavailability of at least one buffer in the respective buffers to be acquired for the first ones of the processing threads. Disclosed example thread schedulers also include a thread execution manager to initiate execution of second ones of the processing threads that are not identified as stalled.

Abstract: A method for testing an imaging subsystem of a system-on-a-chip (SOC) is provided that includes executing imaging subsystem test software instructions periodically on a processor of the SOC, receiving reference image data in the imaging subsystem responsive to the executing of the test software instructions, performing image signal processing on the reference image data by the imaging subsystem to generate processed reference image data, and using the processed reference image data by the test software instructions to verify whether or not the imaging subsystem is operating correctly.

Abstract: Method and system to improve the performance of a video encoder. The method includes processing an initial video signal in a front-end image pre-processor to obtain a processed video signal and processor information respecting the signal, providing the processed video signal and the processor information to a video encoder, and encoding the video signal in the video encoder according to the processor information to provide an encoded video signal for storage. The system includes a video pre-processor connectable to receive an initial video signal. The video encoder in communication with the video pre-processor receives a processed video signal and a processor information. A storage medium in communication with the video encoder stores an encoded video signal.

Abstract: Method and system to improve the performance of a video encoder. The method includes processing an initial video signal in a front-end image pre-processor to obtain a processed video signal and processor information respecting the signal, providing the processed video signal and the processor information to a video encoder, and encoding the video signal in the video encoder according to the processor information to provide an encoded video signal for storage. The system includes a video pre-processor connectable to receive an initial video signal. The video encoder in communication with the video pre-processor receives a processed video signal and a processor information. A storage medium in communication with the video encoder stores an encoded video signal.

Abstract: A method for testing an imaging subsystem of a system-on-a-chip (SOC) is provided that includes executing imaging subsystem test software instructions periodically on a processor of the SOC, receiving reference image data in the imaging subsystem responsive to the executing of the test software instructions, performing image signal processing on the reference image data by the imaging subsystem to generate processed reference image data, and using the processed reference image data by the test software instructions to verify whether or not the imaging subsystem is operating correctly.