Patents by Inventor Kedar Janardan Dhori
Kedar Janardan Dhori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230008833Abstract: SRAM cells are connected in columns by bit lines and connected in rows by first and second word lines coupled to first and second data storage sides of the SRAM cells. First the first word lines are actuated in parallel and then next the second word lines are actuated in parallel in first and second phases, respectively, of an in-memory compute operation. Bit line voltages in the first and second phases are processed to generate an in-memory compute operation decision. A low supply node reference voltage for the SRAM cells is selectively modulated between a ground voltage and a negative voltage. The first data storage side receives the negative voltage and the second data storage side receives the ground voltage during the second phase. Conversely, the second data storage side receives the negative voltage and the first data storage side receives the ground voltage during the first phase.Type: ApplicationFiled: June 27, 2022Publication date: January 12, 2023Applicant: STMicroelectronics International N.V.Inventors: Harsh RAWAT, Kedar Janardan DHORI, Promod KUMAR, Nitin CHAWLA, Manuj AYODHYAWASI
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Publication number: 20230008275Abstract: An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. Each row includes a word line drive circuit powered by an adaptive supply voltage. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A voltage generator circuit generates the adaptive supply voltage for powering the word line drive circuits during the simultaneous actuation. A level of the adaptive supply voltage is modulated dependent on integrated circuit process and/or temperature conditions in order to optimize word line underdrive performance and inhibit unwanted memory cell data flip.Type: ApplicationFiled: June 20, 2022Publication date: January 12, 2023Applicant: STMicroelectronics International N.V.Inventors: Kedar Janardan DHORI, Nitin CHAWLA, Promod KUMAR, Manuj AYODHYAWASI, Harsh RAWAT
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Publication number: 20230009329Abstract: A circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates, through a word line driver circuit for each row, word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A bit line precharge circuit generates a precharge voltage for application to each pair of bit lines. The precharge voltage has a first voltage level (not greater than a positive supply voltage for the SRAM cells) when the memory array is operating in a data read/write mode. The precharge voltage has a second voltage level (greater than the first voltage level) in advance of the simultaneous actuation of the word lines for the in-memory compute operation.Type: ApplicationFiled: June 27, 2022Publication date: January 12, 2023Applicant: STMicroelectronics International N.V.Inventors: Harsh RAWAT, Kedar Janardan DHORI, Promod KUMAR, Nitin CHAWLA, Manuj AYODHYAWASI
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Publication number: 20220130454Abstract: A static random access memory (SRAM) device disclosed herein includes an array of SRAM cells powered between first and second voltages. A reference voltage generator generates a reference voltage that is proportional to absolute temperature, with a magnitude curve of the reference voltage being based upon a control word. A low dropout amplifier sets and maintains the second voltage as being equal to the reference voltage. Control circuitry generates the control word based upon process variation information about the SRAM device. In one instance, the control circuitry monitors a canary bit-cell and increments the control word, to thereby increase the magnitude curve of the reference voltage, until the canary bit-cell fails. In another instance, the control circuitry measures the oscillation frequency of a ring oscillator, and selects the control word based upon the measured oscillation frequency.Type: ApplicationFiled: September 23, 2021Publication date: April 28, 2022Applicant: STMicroelectronics International N.V.Inventor: Kedar Janardan DHORI
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Publication number: 20220122657Abstract: An integrated circuit includes a memory array. The memory array includes a plurality of bitlines. The bitlines are each coupled to a respective local I/O circuit. All of the local I/O circuits are coupled to a global I/O circuit. Each local I/O circuit includes a first sensing stage for reading data from the memory cell. The global I/O circuit includes a second sensing stage for reading data from the memory cell.Type: ApplicationFiled: October 5, 2021Publication date: April 21, 2022Applicant: STMicroelectronics International N.V.Inventor: Kedar Janardan DHORI
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Publication number: 20210327501Abstract: A static random access memory (SRAM) architecture includes a first column of SRAM cells coupled between a first bit line and a first complementary bit line, and first write circuit for the first column. The first write circuit includes a first latch receiving first input data and providing complementary outputs to the first bit line and the first complementary bit line. The first write circuit has a latchable output state driving the first bit line and first complementary bit line, and the latchable output state does not change between consecutive write operations if a state of the received first input data does not change between the consecutive write operations, but does change between the consecutive write operations if the state of the received first input data changes between the consecutive write operations.Type: ApplicationFiled: April 2, 2021Publication date: October 21, 2021Applicant: STMicroelectronics International N.V.Inventor: Kedar Janardan DHORI
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Publication number: 20210193669Abstract: A memory cell including a set of active regions that overlay a set of gate regions to form a pair of cross-coupled inverters. A first active region extends along a first axis. A first gate region extends transversely to the first active region and overlays the first active region to form a first transistor of the pair of cross-coupled inverters. A second gate region extends transversely to the first active region and overlays the first active region to form a second transistor of the pair of cross-coupled inverters. A second active region extends along a second axis and overlays the first gate region to form a third transistor of the pair of cross-coupled inverters. A fourth active region extending along a third axis and overlays a gate region to form a transistor of a read port.Type: ApplicationFiled: December 10, 2020Publication date: June 24, 2021Applicant: STMicroelectronics International N.V.Inventors: Shafquat Jahan AHMED, Kedar Janardan DHORI
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Publication number: 20210181828Abstract: Systems and devices are provided to enable granular control over a retention or active state of each of a plurality of memory circuits, such as a plurality of memory cell arrays, within a memory. Each respective memory array of the plurality of memory arrays is coupled to a respective ballast driver and a respective active memory signal switch for the respective memory array. One or more voltage regulators are coupled to a ballast driver gate node and to a bias node of at least one of the respective memory arrays. In operation, the respective active memory signal switch for a respective memory array causes the respective memory array to transition between an active state for the respective memory array and a retention state for the respective memory array.Type: ApplicationFiled: December 3, 2020Publication date: June 17, 2021Inventors: Nitin CHAWLA, Anuj GROVER, Giuseppe DESOLI, Kedar Janardan DHORI, Thomas BOESCH, Promod KUMAR
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Patent number: 10224097Abstract: Read stability of a memory is enhanced in low voltage operation mode by selectively boosting a cell supply voltage for a row of memory cells. The boosted voltage results from a capacitive coupling to the word line in that row. The capacitive coupling is implemented by running the metal line of the power supply line for the cell supply voltage and the metal line for the word line adjacent to each other in a common metallization level. The selective voltage boost is controlled in response to operation of a modified memory cell exhibiting a deteriorated write margin. An output of the modified memory cell is compared to a threshold to generate a signal for controlling the selective voltage boost. Word line under-voltage circuitry is further provided to control application of an under-voltage to the word line.Type: GrantFiled: March 1, 2018Date of Patent: March 5, 2019Assignee: STMicroelectronics International N.V.Inventors: Ashish Kumar, Vinay Kumar, Kedar Janardan Dhori
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Publication number: 20180190346Abstract: Read stability of a memory is enhanced in low voltage operation mode by selectively boosting a cell supply voltage for a row of memory cells. The boosted voltage results from a capacitive coupling to the word line in that row. The capacitive coupling is implemented by running the metal line of the power supply line for the cell supply voltage and the metal line for the word line adjacent to each other in a common metallization level. The selective voltage boost is controlled in response to operation of a modified memory cell exhibiting a deteriorated write margin. An output of the modified memory cell is compared to a threshold to generate a signal for controlling the selective voltage boost. Word line under-voltage circuitry is further provided to control application of an under-voltage to the word line.Type: ApplicationFiled: March 1, 2018Publication date: July 5, 2018Applicant: STMicroelectronics International N.V.Inventors: Ashish Kumar, Vinay Kumar, Kedar Janardan Dhori
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Patent number: 9940997Abstract: Read stability of a memory is enhanced in low voltage operation mode by selectively boosting a cell supply voltage for a row of memory cells. The boosted voltage results from a capacitive coupling to the word line in that row. The capacitive coupling is implemented by running the metal line of the power supply line for the cell supply voltage and the metal line for the word line adjacent to each other in a common metallization level. The selective voltage boost is controlled in response to operation of a modified memory cell exhibiting a deteriorated write margin. An output of the modified memory cell is compared to a threshold to generate a signal for controlling the selective voltage boost. Word line under-voltage circuitry is further provided to control application of an under-voltage to the word line.Type: GrantFiled: March 2, 2017Date of Patent: April 10, 2018Assignee: STMicroelectronics International N.V.Inventors: Ashish Kumar, Vinay Kumar, Kedar Janardan Dhori
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Patent number: 9865333Abstract: A memory circuit includes a wordline, memory cells connected to the wordline and a wordline driver circuit including a p-channel pull-up transistor. The memory circuit further includes a read assist circuit including an n-channel pull-down transistor having a source-drain path connected between the wordline and a ground node and an n-channel diode-connected transistor having a source-drain path connected between a positive supply node and a gate terminal of the n-channel pull-down transistor. The n-channel diode-connected transistor is configured to apply a biasing voltage to the gate terminal of the n-channel pull-down transistor that is a relatively lower voltage for relatively lower temperatures and a relatively higher voltage for relatively higher temperatures.Type: GrantFiled: April 19, 2016Date of Patent: January 9, 2018Assignee: STMicroelectronics International N.V.Inventors: Kedar Janardan Dhori, Ashish Kumar, Hitesh Chawla, Praveen Kumar Verma
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Publication number: 20170301396Abstract: A memory circuit includes a wordline, memory cells connected to the wordline and a wordline driver circuit including a p-channel pull-up transistor. The memory circuit further includes a read assist circuit including an n-channel pull-down transistor having a source-drain path connected between the wordline and a ground node and an n-channel diode-connected transistor having a source-drain path connected between a positive supply node and a gate terminal of the n-channel pull-down transistor. The n-channel diode-connected transistor is configured to apply a biasing voltage to the gate terminal of the n-channel pull-down transistor that is a relatively lower voltage for relatively lower temperatures and a relatively higher voltage for relatively higher temperatures.Type: ApplicationFiled: April 19, 2016Publication date: October 19, 2017Applicant: STMicroelectronics International N.V.Inventors: Kedar Janardan Dhori, Ashish Kumar, Hitesh Chawla, Praveen Kumar Verma
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Patent number: 9685209Abstract: A sense amplifier enable signal generating circuit includes an input coupled to a dummy bit line of a memory. A voltage comparator circuit compares a voltage on the dummy bit line to a threshold voltage and generates an output signal when the voltage falls below that threshold voltage. A multi-bit counter circuit counts a count value in response to the output signal. A pull-up circuit pulls up the voltage on the dummy bit line in response to the output signal. A count comparator circuit compares the count value to a count threshold and generates a sense amplifier enable signal when the count value equals the count threshold.Type: GrantFiled: April 19, 2016Date of Patent: June 20, 2017Assignee: STMicroelectronics International N.V.Inventors: Kedar Janardan Dhori, Vinay Kumar, Ashish Kumar
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Patent number: 9208040Abstract: Repair control logic for a safe memory having redundant elements is provided. The repair control logic includes comparison logic including, for each bit slice of a memory array, a comparator circuit configured to determine whether a location value of an associated bit slice of the memory array is greater than a location value of a defective bit slice of the memory array, and data switching logic including, for each bit slice of the memory array, a switching circuit, responsive to a determination that the location value of the associated bit slice is greater than the location value of the defective bit slice, to switch data from the associated bit slice to an adjacent bit slice of the memory array.Type: GrantFiled: April 30, 2014Date of Patent: December 8, 2015Assignee: STMicroelectronics International N.V.Inventors: Harsh Rawat, Kedar Janardan Dhori, Vinay Kumar, PraveenKumar Verma
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Publication number: 20150317225Abstract: Repair control logic for a safe memory having redundant elements is provided. The repair control logic includes comparison logic including, for each bit slice of a memory array, a comparator circuit configured to determine whether a location value of an associated bit slice of the memory array is greater than a location value of a defective bit slice of the memory array, and data switching logic including, for each bit slice of the memory array, a switching circuit, responsive to a determination that the location value of the associated bit slice is greater than the location value of the defective bit slice, to switch data from the associated bit slice to an adjacent bit slice of the memory array.Type: ApplicationFiled: April 30, 2014Publication date: November 5, 2015Applicant: STMicroelectronics International N.V.Inventors: Harsh Rawat, Kedar Janardan Dhori, Vinay Kumar, PraveenKumar Verma
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Patent number: 8154936Abstract: A single-ended bit line based storage system. The storage system includes a first set of storage cells, a second set of storage cells, a first set of reference storage cells, a second set of reference storage cells, and a differential sensing block. The memory core is split vertically in half vertically to form the first set of storage cells and the second set of storage cells. The first set of reference storage cells provides a discharge rate lower than the discharge rate of said first set and second set of storage cells for storing data. The second set of reference storage cells provides a discharge rate lower than the discharge rate of said first set and second set of storage cells for storing data. The differential sensing block is coupled to the first set of storage cells and the second set of storage cells for generating an output data signal on receiving a control signal.Type: GrantFiled: December 30, 2008Date of Patent: April 10, 2012Assignee: STMicroelectronics Pvt. Ltd.Inventor: Kedar Janardan Dhori