Patents by Inventor Kedar Patel

Kedar Patel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10287590
    Abstract: The invention provides methods for introducing co-varying paired nucleic acids into a vector such under separate transcriptional control. An oligonucleotide is synthesized including the paired nucleic acids. The oligonucleotide is then assembled with a spacer nucleic acid encoding a promoter. After assembly the spacer nucleic acid is to one side of the oligonucleotide encoding the paired segments. However, on circularization of the assembled nucleic acid and cleavage between the DNA segments the spacer oligonucleotide and its components now occur between the paired segments. The resulting nucleic acid can now be cloned into a vector with a single step, such that each of the paired nucleic acid segments is linked to its own promoter. The present method can readily be extended to library screening without proportionately increasing the effort.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: May 14, 2019
    Assignee: DNA2.0, INC.
    Inventors: Jeremy Minshull, Sridhar Govindrajan, Kedar Patel
  • Patent number: 9548348
    Abstract: Non-volatile memory cells including complimentary metal-oxide-semiconductor transistors and embedded ferroelectric capacitor and methods of forming the same are described. In one embodiment, the method includes forming on a surface of a substrate a gate level including a gate stack of a MOS transistor, a first dielectric layer overlying the MOS transistor and a first contact extending through the first dielectric layer from a top surface thereof to a diffusion region of the MOS transistor. A local interconnect (LI) layer is deposited over the top surface of the first dielectric layer and the first contact, a ferro stack including a bottom electrode, a top electrode and ferroelectric layer there between deposited over the LI layer, and the ferro stack and the LI layer patterned to form a ferroelectric capacitor and a LI through which the bottom electrode is electrically coupled to the diffusion region of the MOS transistor.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: January 17, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventors: Shan Sun, Krishnaswamy Ramkumar, Thomas Davenport, Kedar Patel
  • Publication number: 20150225730
    Abstract: The invention provides methods for introducing co-varying paired nucleic acids into a vector such under separate transcriptional control. An oligonucleotide is synthesized including the paired nucleic acids. The oligonucleotide is then assembled with a spacer nucleic acid encoding a promoter. After assembly the spacer nucleic acid is to one side of the oligonucleotide encoding the paired segments. However, on circularization of the assembled nucleic acid and cleavage between the DNA segments the spacer oligonucleotide and its components now occur between the paired segments. The resulting nucleic acid can now be cloned into a vector with a single step, such that each of the paired nucleic acid segments is linked to its own promoter. The present method can readily be extended to library screening without proportionately increasing the effort.
    Type: Application
    Filed: December 24, 2014
    Publication date: August 13, 2015
    Inventors: JEREMY MINSHULL, SRIDHAR GOVINDRAJAN, KEDAR PATEL
  • Publication number: 20150004718
    Abstract: Non-volatile memory cells including complimentary metal-oxide-semiconductor transistors and embedded ferroelectric capacitor and methods of forming the same are described. In one embodiment, the method includes forming on a surface of a substrate a gate level including a gate stack of a MOS transistor, a first dielectric layer overlying the MOS transistor and a first contact extending through the first dielectric layer from a top surface thereof to a diffusion region of the MOS transistor. A local interconnect (LI) layer is deposited over the top surface of the first dielectric layer and the first contact, a ferro stack including a bottom electrode, a top electrode and ferroelectric layer there between deposited over the LI layer, and the ferro stack and the LI layer patterned to form a ferroelectric capacitor and a LI through which the bottom electrode is electrically coupled to the diffusion region of the MOS transistor.
    Type: Application
    Filed: December 17, 2013
    Publication date: January 1, 2015
    Applicant: Cypress Semiconductor Corporation
    Inventors: Shan SUN, Krishnaswamy RAMKUMAR, Thomas DAVENPORT, Kedar PATEL
  • Publication number: 20120208232
    Abstract: Compositions and methods are provided for the cell-free synthesis of active reprogramming factor polypeptides. The reprogramming factors may be synthesized as fusion proteins comprising a permeant domain, such as polyarginme. The cell free-synthesis may be conducted at about 25 C in a bacterial cell extract from genetically alterd cells having decreased endogenous protease activity Further, the proteins may comprise a fusion partner which enhances solubility and may be refolded on a column.
    Type: Application
    Filed: July 14, 2010
    Publication date: August 16, 2012
    Inventors: William Yang, Kedar Patel, Yohannes T. Ghebremariam, Ji Eun Lee, Hann-Chung Wong, John P. Cooke, James Robert Swartz
  • Publication number: 20050227316
    Abstract: The invention provides strategies, methods, vectors, reagents, and systems for production of synthetic genes, production of libraries of such genes, and manipulation and characterization of the genes and corresponding encoded polypeptides. In one aspect, the synthetic genes can encode polyketide synthase polypeptides and facilitate production of therapeutically or commercially important polyketide compounds.
    Type: Application
    Filed: April 7, 2004
    Publication date: October 13, 2005
    Applicant: Kosan Biosciences, Inc.
    Inventors: Daniel Santi, Sarah Kodumal, Ralph Reid, Kedar Patel
  • Patent number: 6940109
    Abstract: A semiconductor device comprises two transistors where a gate electrode of one transistor and source or drain of another transistor are located in the same rail. A monolithic three dimensional array contains a plurality of such devices. The transistors in different levels of the array preferably have a different orientation.
    Type: Grant
    Filed: February 18, 2004
    Date of Patent: September 6, 2005
    Assignee: Matrix Semiconductor, Inc.
    Inventors: Kedar Patel, Alper Ilkbahar, Roy Scheuerlein, Andrew J. Walker
  • Publication number: 20050026894
    Abstract: 2-Desmethyl ansamycins having a structure according to formula I, where R1, R2, R3, R4, R5 and R6 are as defined herein, and other 2-desmethyl ansamycins are useful as antiproliferative agents.
    Type: Application
    Filed: June 14, 2004
    Publication date: February 3, 2005
    Inventors: Zong-Qiang Tian, Robert McDaniel, David Myles, Kedar Patel, Misty Piagentini, Zhan Wang
  • Patent number: 6833330
    Abstract: A method of making a semiconductor structure includes sealing a gate layer by wet oxidation. The gate layer is on a substrate containing isolation regions. Semiconductor devices prepared from the semiconductor structure exhibits reduced inverse narrow width effects.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: December 21, 2004
    Assignee: Cypress Semiconductor Corporation
    Inventors: Jeffrey T. Watt, Kedar Patel
  • Publication number: 20040159860
    Abstract: A semiconductor device comprises two transistors where a gate electrode of one transistor and source or drain of another transistor are located in the same rail. A monolithic three dimensional array contains a plurality of such devices. The transistors in different levels of the array preferably have a different orientation.
    Type: Application
    Filed: February 18, 2004
    Publication date: August 19, 2004
    Applicant: Matrix Semiconductor, Inc.
    Inventors: Kedar Patel, Alper Ilkbahar, Roy Scheuerlein, Andrew J. Walker
  • Patent number: 6737675
    Abstract: A semiconductor device comprises two transistors where a gate electrode of one transistor and source or drain of another transistor are located in the same rail. A monolithic three dimensional array contains a plurality of such devices. The transistors in different levels of the array preferably have a different orientation.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: May 18, 2004
    Assignee: Matrix Semiconductor, Inc.
    Inventors: Kedar Patel, Alper Ilkbahar, Roy Scheuerlein, Andrew J. Walker
  • Publication number: 20040000679
    Abstract: A semiconductor device comprises two transistors where a gate electrode of one transistor and source or drain of another transistor are located in the same rail. A monolithic three dimensional array contains a plurality of such devices. The transistors in different levels of the array preferably have a different orientation.
    Type: Application
    Filed: June 27, 2002
    Publication date: January 1, 2004
    Applicant: Matrix Semiconductor, Inc.
    Inventors: Kedar Patel, Alper Ilkbahar, Roy Scheuerlein, Andrew J. Walker
  • Patent number: 6667224
    Abstract: A method of making a semiconductor structure includes sealing a gate layer by wet oxidation. The gate layer is on a substrate containing isolation regions. Semiconductor devices prepared from the semiconductor structure exhibits reduced inverse narrow width effects.
    Type: Grant
    Filed: August 13, 2001
    Date of Patent: December 23, 2003
    Assignee: Cypress Semiconductor Corp.
    Inventors: Jeffrey T. Watt, Kedar Patel