Abstract: Methods and apparatus are described for detecting anomalies in a clock signal. Example methods include sensing a clock signal that exhibits alternating phases during normal operation; responsive to sensing the start of a first phase, generating a pulse; and if the pulse terminates before sensing the end of the first phase, asserting a clock stopped detection signal. Example clock anomaly detection apparatus includes a clock signal input for coupling to a clock signal that, during normal operation, oscillates between first and second clock states. An anomaly detection output is asserted if the clock signal remains in the first clock state longer than a first phase expected duration or remains in the second clock state longer than a second phase expected duration.

Abstract: Techniques are described for detecting an electromagnetic (“EM”) fault injection attack directed toward circuitry in a target digital system. In various embodiments, a first node may be coupled to first driving circuitry, and a second node may be coupled to second driving circuitry. The driving circuitry is implemented in a manner such that a logic state on the second node has greater sensitivity to an EM pulse than has a logic state on the first node. Comparison circuitry may be coupled to the first and to the second nodes to assert an attack detection output responsive to sensing a logic state on the second node that is unexpected relative to a logic state on the first node.

Abstract: Methods and structures are described for detecting clock anomalies, including anomalies in which the clock oscillates at a faster than expected rate or exhibits a shorter than expected clock phase instance. Example methods include starting a timer responsive to the start of a clock phase, wherein the timer duration is shorter than an expected duration of the clock phase. If the clock phase ends before the timer expires, a fast clock detection signal is asserted. Example structures include fast clock detection logic coupled to a clock signal. The logic includes a timer, circuitry to start the timer responsive to the clock signal entering a monitored phase, and error detection circuitry to assert a fast clock detection output if the monitored phase ends before the timer expires. In some embodiments, the timer duration may be based on a measured duration of a previous clock phase.

Abstract: Methods and structures are described for detecting clock anomalies. Example methods include measuring a duration of a first phase of the clock signal, monitoring a duration of a second phase of the clock signal, and determining whether the duration of the second phase has exceeded the measured duration of the first phase. If so, a clock stop detection signal is asserted. Example structures include a detector circuit having an input for sensing the clock signal. The circuit is operable to measure a duration of a first clock phase instance, to monitor a duration of a second clock phase instance, and to assert an output if the duration of the second clock phase instance exceeds the measured duration of the first clock phase instance.

Abstract: Methods and apparatus are described for detecting anomalies in a clock signal. Example methods include sensing a clock signal that exhibits alternating phases during normal operation; responsive to sensing the start of a first phase, generating a pulse; and if the pulse terminates before sensing the end of the first phase, asserting a clock stopped detection signal. Example clock anomaly detection apparatus includes a clock signal input for coupling to a clock signal that, during normal operation, oscillates between first and second clock states. An anomaly detection output is asserted if the clock signal remains in the first clock state longer than a first phase expected duration or remains in the second clock state longer than a second phase expected duration.

Abstract: Methods and structures are described for detecting clock anomalies. Example methods include measuring a duration of a first phase of the clock signal, monitoring a duration of a second phase of the clock signal, and determining whether the duration of the second phase has exceeded the measured duration of the first phase. If so, a clock stop detection signal is asserted. Example structures include a detector circuit having an input for sensing the clock signal. The circuit is operable to measure a duration of a first clock phase instance, to monitor a duration of a second clock phase instance, and to assert an output if the duration of the second clock phase instance exceeds the measured duration of the first clock phase instance.

Abstract: A circuit includes a supply power detector in a first power domain and a ratioed inverter in the first power domain or a second, different power domain. The supply power detector includes an output coupled to an input of the ratioed inverter, and an output of the ratioed inverter provides a power sequencing signal for the second power domain.

Abstract: A glitch detection circuit includes a supply power glitch detection circuit in a first power domain and a ratioed inverter in a second power domain different than the first power domain. The glitch detection circuit may be used in a method to detect cross-power domain glitches.