Abstract: A scan driver includes stage circuits, wherein each of the stage circuits includes a first transistor, wherein a first electrode thereof is coupled to a first node, a second electrode thereof is coupled to an input carry line, and a gate electrode thereof is coupled to a first clock line; and a capacitor, wherein a first electrode thereof is coupled to the first node and a second electrode thereof is coupled to a second node, wherein the second node is coupled to an output carry line, and the second node is selectively coupled to one of a first power voltage line and a second power voltage line.

Abstract: A display apparatus is disclosed, which includes a pixel. The pixel includes first through fifth transistors and a light emitting element. The first transistor includes a control electrode electrically connected to a first node, an input electrode that receives a first power voltage and an output electrode electrically connected to the light emitting element. The second transistor includes a control electrode that receives a scan signal, an input electrode that receives a grayscale data voltage and an output electrode electrically connected to a second node. The third transistor includes a control electrode electrically connected to the second node, an input electrode that receives a reference voltage and an output electrode electrically connected to the first node. The fourth transistor includes a control electrode that receives the scan signal, an input electrode that receives a bias data voltage and an output electrode electrically connected to the first node.

Abstract: A display apparatus is disclosed, which includes a pixel. The pixel includes first through fifth transistors and a light emitting element. The first transistor includes a control electrode electrically connected to a first node, an input electrode that receives a first power voltage and an output electrode electrically connected to the light emitting element. The second transistor includes a control electrode that receives a scan signal, an input electrode that receives a grayscale data voltage and an output electrode electrically connected to a second node. The third transistor includes a control electrode electrically connected to the second node, an input electrode that receives a reference voltage and an output electrode electrically connected to the first node. The fourth transistor includes a control electrode that receives the scan signal, an input electrode that receives a bias data voltage and an output electrode electrically connected to the first node.

Abstract: A display device includes a scan write line for receiving a scan write signal, a first driving voltage line for receiving a first driving voltage, a first data line for receiving first data voltages, a second data line for receiving second data voltages, and a sub-pixel connected to the scan write line, the first data line, the second data line, and the first driving voltage line, wherein the sub-pixel includes a light emitting element connected to the first driving voltage line, a constant current generator configured to apply a driving current to the light emitting element according to a first data voltage among the first data voltages of the first data line, and a light emission period controller configured to control a light emission period of the light emitting element according to a second data voltage among the second data voltages of the second data line.

Abstract: A display device includes: a plurality of pixels, each of which is connected to a corresponding one of a plurality of scan lines, and a scan driver including a plurality of stages, each of which supplies a scan signal to a corresponding one of the scan lines, each of the stages includes: a node controller which supplies a second output signal of a previous stage to a first node based on an input signal of a first clock terminal or a first output signal of the previous stage, a first inverter connected between the first node and a second node, a buffer which supplies a voltage of the second node to a first output terminal based on an input signal of a second clock terminal, and a second inverter connected between the first output terminal and a second output terminal.

Abstract: A display device includes a scan write line for receiving a scan write signal, a first driving voltage line for receiving a first driving voltage, a first data line for receiving first data voltages, a second data line for receiving second data voltages, and a sub-pixel connected to the scan write line, the first data line, the second data line, and the first driving voltage line, wherein the sub-pixel includes a light emitting element connected to the first driving voltage line, a constant current generator configured to apply a driving current to the light emitting element according to a first data voltage among the first data voltages of the first data line, and a light emission period controller configured to control a light emission period of the light emitting element according to a second data voltage among the second data voltages of the second data line.

Abstract: A scan driver includes stage circuits, wherein each of the stage circuits includes a first transistor, wherein a first electrode thereof is coupled to a first node, a second electrode thereof is coupled to an input carry line, and a gate electrode thereof is coupled to a first clock line; and a capacitor, wherein a first electrode thereof is coupled to the first node and a second electrode thereof is coupled to a second node, wherein the second node is coupled to an output carry line, and the second node is selectively coupled to one of a first power voltage line and a second power voltage line.

Abstract: An emission signal driver comprises stages connected to emission lines. Each of the stages includes a node controller which supplies a start signal or a carry signal, which is input to a start terminal, to a first node in response to a clock signal input to a clock terminal, a first inverter connected between the first node and a second node, and a second inverter connected between the second node and an output terminal.

Abstract: A display device includes: a plurality of pixels, each of which is connected to a corresponding one of a plurality of scan lines, and a scan driver including a plurality of stages, each of which supplies a scan signal to a corresponding one of the scan lines, each of the stages includes: a node controller which supplies a second output signal of a previous stage to a first node based on an input signal of a first clock terminal or a first output signal of the previous stage, a first inverter connected between the first node and a second node, a buffer which supplies a voltage of the second node to a first output terminal based on an input signal of a second clock terminal, and a second inverter connected between the first output terminal and a second output terminal.

Abstract: An emission signal driver comprises stages connected to emission lines. Each of the stages includes a node controller which supplies a start signal or a carry signal, which is input to a start terminal, to a first node in response to a clock signal input to a clock terminal, a first inverter connected between the first node and a second node, and a second inverter connected between the second node and an output terminal.

Abstract: Disclosed are an inverter, a NAND gate, and a NOR gate. The inverter includes: a pull-up unit constituted by a second thin film transistor outputting a first power voltage to an output terminal according to a voltage applied to a gate; a pull-down unit constituted by a fifth thin film transistor outputting a ground voltage to the output terminal according to an input signal applied to a gate; and a pull-up driver applying a second power voltage or the ground voltage to the gate of the second thin film transistor according to the input signal.

Abstract: Provided is a gate driver circuit. The gate driver circuit includes a plurality of sequentially connected stages, and each of stages includes an input unit including two input transistors forming diode connection, a pull-up unit including a pull-up transistor and a bootstrap capacitor, and first and second pull-down units each including two transistors. According to embodiments, an input capacitor is further included which is connected to a node between the input unit and the pull-up unit. In addition, a carry unit is further included which is connected to an output terminal and formed to transmit an output signal in a high state or a low state to a next stage.

Abstract: Provided is a single input level shifter. The single input level shifter includes: an input unit applying a power voltage to a first node in response to an input signal and applying the input signal to a second node in response to a reference signal; a bootstrapping unit applying the power voltage to the second node according to a voltage level of the first node; and an output unit applying the input signal to an output terminal in response to the reference signal and applying the power voltage to the output terminal according to the voltage level of the first node, wherein the bootstrapping unit includes a capacitor between the first and second nodes, and when the input signal is shifted from a first voltage level to a second voltage level, the bootstrapping unit raises the voltage level of the first node to a level higher than the power voltage.

Abstract: Disclosed is a DC voltage conversion circuit of a liquid crystal display apparatus, including: a main pumping circuit including a plurality of thin film transistors and configured to output voltage for driving a liquid crystal display apparatus when the plurality of thin film transistors are alternately turned on or off; and a switch control signal generator configured to control voltages applied to gates of the plurality of thin film transistors by inversion of a clock signal, in which each thin film transistor is turned on when positive gate-source voltage is applied thereto, and turned off when negative gate-source voltage is applied thereto.

Abstract: Disclosed are an inverter, a NAND gate, and a NOR gate. The inverter includes: a pull-up unit constituted by a second thin film transistor outputting a first power voltage to an output terminal according to a voltage applied to a gate; a pull-down unit constituted by a fifth thin film transistor outputting a ground voltage to the output terminal according to an input signal applied to a gate; and a pull-up driver applying a second power voltage or the ground voltage to the gate of the second thin film transistor according to the input signal.

Abstract: A panel structure includes a transistor including a gate electrode, a source electrode and a drain electrode, a power source line, a pixel electrode, and one or more contact plugs formed of a same material as the pixel electrode and electrically connecting the power source line and the source electrode.

Abstract: Provided is a single input level shifter. The single input level shifter includes: an input unit applying a power voltage to a first node in response to an input signal and applying the input signal to a second node in response to a reference signal; a bootstrapping unit applying the power voltage to the second node according to a voltage level of the first node; and an output unit applying the input signal to an output terminal in response to the reference signal and applying the power voltage to the output terminal according to the voltage level of the first node, wherein the bootstrapping unit includes a capacitor between the first and second nodes, and when the input signal is shifted from a first voltage level to a second voltage level, the bootstrapping unit raises the voltage level of the first node to a level higher than the power voltage.

Abstract: Disclosed are an inverter, a NAND gate, and a NOR gate. The inverter includes: a pull-up unit constituted by a second thin film transistor outputting a first power voltage to an output terminal according to a voltage applied to a gate; a pull-down unit constituted by a fifth thin film transistor outputting a ground voltage to the output terminal according to an input signal applied to a gate; and a pull-up driver applying a second power voltage or the ground voltage to the gate of the second thin film transistor according to the input signal.

Abstract: Disclosed are an inverter, a NAND gate, and a NOR gate. The inverter includes: a pull-up unit constituted by a second thin film transistor outputting a first power voltage to an output terminal according to a voltage applied to a gate; a pull-down unit constituted by a fifth thin film transistor outputting a ground voltage to the output terminal according to an input signal applied to a gate; and a pull-up driver applying a second power voltage or the ground voltage to the gate of the second thin film transistor according to the input signal.

Abstract: Disclosed are an inverter, a NAND gate, and a NOR gate. The inverter includes: a pull-up unit constituted by a second thin film transistor outputting a first power voltage to an output terminal according to a voltage applied to a gate; a pull-down unit constituted by a fifth thin film transistor outputting a ground voltage to the output terminal according to an input signal applied to a gate; and a pull-up driver applying a second power voltage or the ground voltage to the gate of the second thin film transistor according to the input signal.