Abstract: A memory card is disclosed including first and second host interfaces facilitating the communication of data between the memory card and a host using, respectively, first and second protocols, wherein the first protocol defines low-speed operations and the second protocol defines high-speed operations for the memory card. The second host interface is only enabled in response to an indication by the host device of a high-speed memory card operation.

Abstract: A hub, a memory module, a memory system, and methods for reading and writing to the same. In a test mode, memory module, memory device or memory unit identifying information may be ignored, so that all memory modules, memory devices or memory units may be test written or test read. Ignoring the memory identifying information may permit all the memory modules, memory devices or memory units to be written or read simultaneously, thereby decreasing test time.

Abstract: A memory device includes a high speed port, a low speed port, at least a first memory bank, a first register, and a multiplexer. The at least first memory bank is shared by the high speed port and the low speed port. The first register store information that indicates which one of the ports has permission to access the first memory bank. The multiplexer connects one of the high speed port or the low speed port to the first memory bank, in response to the information stored in the first register.

Abstract: An integrated circuit memory device may include a memory cell array and a plurality of data input/output pins. The plurality of data input/output pins may be configured to receive data from a memory controller to be written to the memory cell array during a data write operation, and the data input/output pins may be further configured to provide data to the memory controller from the memory cell array during a data read operation. A mode register may be configured to store information defining an operational characteristic of the memory device, and the mode register may be configured to be set using the data input/output bus. Related methods, systems, and additional devices are also discussed.

Abstract: An integrated circuit memory device may include a memory cell array and a plurality of data input/output pins. The plurality of data input/output pins may be configured to receive data from a memory controller to be written to the memory cell array during a data write operation, and the data input/output pins may be further configured to provide data to the memory controller from the memory cell array during a data read operation. A mode register may be configured to store information defining an operational characteristic of the memory device, and the mode register may be configured to be set using the data input/output bus. Related methods, systems, and additional devices are also discussed.

Abstract: A memory module may include a plurality of memory devices coupled to a memory controller over a same command/address bus. Methods of controlling such a memory module may include providing a mode register set command from the memory controller to each of the integrated circuit memory devices over the command/address bus during a mode register set operation. A disable signal may be provided from the memory controller to a first one of the integrated circuit memory devices over a signal line between the memory controller and the first integrated circuit memory device to thereby disable implementation of the mode register set command for the first integrated circuit memory device during the mode register set operation.

Abstract: A memory module includes a body with a plurality of memory chips mounted thereon and an elongated connector protruding from the body. The elongated connector includes a plurality of single in-line memory module (SIMM)-type contacts at first portions along an edge thereof and a plurality of dual in-line memory module (DIMM)-type contacts at second portions along the edge thereof. The plurality of SIMM-type contacts may be positioned at opposing end portions of the elongated connector, and the plurality of DIMM-type contacts may be positioned between the opposing end portions. Related memory systems including a system board having a socket therein configured to receive the memory module are also discussed.

Abstract: A memory device includes a high speed port, a low speed port, at least a first memory bank, a first register, and a multiplexer. The at least first memory bank is shared by the high speed port and the low speed port. The first register store information that indicates which one of the ports has permission to access the first memory bank. The multiplexer connects one of the high speed port or the low speed port to the first memory bank, in response to the information stored in the first register.

Abstract: A memory hub control block may be configured to decode a command packet received from a host and determine whether the command packet has designated the memory hub. If the command packet does not designate the memory hub control block, the memory hub control block may transmit a temperature information request signal to at least one of a plurality of semiconductor memory devices coupled to the memory hub, and receive temperature information from one of the plurality of semiconductor memory devices.

Abstract: A memory module may include a plurality of memory devices coupled to a memory controller over a same command/address bus. Methods of controlling such a memory module may include providing a mode register set command from the memory controller to each of the integrated circuit memory devices over the command/address bus during a mode register set operation. A disable signal may be provided from the memory controller to a first one of the integrated circuit memory devices over a signal line between the memory controller and the first integrated circuit memory device to thereby disable implementation of the mode register set command for the first integrated circuit memory device during the mode register set operation.

Abstract: Semiconductor memory devices include a memory cell array, a deserializer, a decoder, a redundancy code checker, a control circuit, a redundancy code generator and a serializer. The deserializer generates a deserialized data by deserializing a first serialized data. The decoder generates a first data, a command signal, an address signal and a first redundancy code by decoding the deserialized data. The redundancy code checker generates a status signal by comparing the first data with the first redundancy code and detects an error in the first data. The control circuit stores the first data in the memory cell array or outputs a second data stored in the memory cell array in response to the command signal and the address signal. The redundancy code generator generates a second redundancy code by using the second data. The serializer generates a second serialized data by serializing the second data and the second redundancy code.

Abstract: Provided is a memory device for high speed communication including a low speed data communication port and a low speed data input/output circuit, and a data communication system using the memory device. The memory device includes a high speed port interface for transmitting or receiving data to or from a host at a high speed, and a low speed port interface for transmitting or receiving data to or from the host at a low speed.

Abstract: A memory module may include a plurality of memory devices coupled to a memory controller over a same command/address bus. Methods of controlling such a memory module may include providing a mode register set command from the memory controller to each of the integrated circuit memory devices over the command/address bus during a mode register set operation. A disable signal may be provided from the memory controller to a first one of the integrated circuit memory devices over a signal line between the memory controller and the first integrated circuit memory device to thereby disable implementation of the mode register set command for the first integrated circuit memory device during the mode register set operation.

Abstract: Provided is a memory device for high speed communication including a low speed data communication port and a low speed data input/output circuit, and a data communication system using the memory device. The memory device includes a high speed port interface for transmitting or receiving data to or from a host at a high speed, and a low speed port interface for transmitting or receiving data to or from the host at a low speed.

Abstract: A memory card is disclosed including first and second host interfaces facilitating the communication of data between the memory card and a host using, respectively, first and second protocols, wherein the first protocol defines low-speed operations and the second protocol defines high-speed operations for the memory card. The second host interface is only enabled in response to an indication by the host device of a high-speed memory card operation.

Abstract: A method of operating a memory system including a plurality of memory devices coupled to a command address bus may be provided. In particular, a first memory device of the plurality of memory devices may be set to a first operating mode, and a second memory device of the plurality of memory devices may be set to a second operating mode different than the first operating mode. In addition, a read/write operation may be performed responsive to a read/write command address signal provided over the command address bus to the plurality of memory devices so that the first memory device operates according to the first operating mode during the read/write operation and so that the second memory device operates according to the second operating mode during the read/write operation. Related systems are also discussed.

Abstract: A method of operating a memory system including a plurality of memory devices coupled to a command address bus may be provided. In particular, a first memory device of the plurality of memory devices may be set to a first operating mode, and a second memory device of the plurality of memory devices may be set to a second operating mode different than the first operating mode. In addition, a read/write operation may be performed responsive to a read/write command address signal provided over the command address bus to the plurality of memory devices so that the first memory device operates according to the first operating mode during the read/write operation and so that the second memory device operates according to the second operating mode during the read/write operation. Related systems are also discussed.

Abstract: A hub for testing memory and methods thereof. The hub may include a test block a test block and a transparent mode block. The test block may be configured to generate a pseudo random pattern based on received memory control information and to write the pseudo random pattern to at least one of a plurality of memory devices in the first operating mode. The transparent mode block may be configured to receive the generated pseudo random pattern from the test block, to read the pseudo random pattern from the at least one of the plurality of memory devices in the first operating mode and to compare the generated pseudo random pattern with the read pseudo random pattern. Also, the hub may perform a transparent mode test on at least one memory device of a memory module with a pseudo random data pattern, the pseudo random data pattern based at least in part on memory control information received from a device not included within the memory module.

Abstract: A memory module may include a plurality of memory devices coupled to a memory controller over a same command/address bus. Methods of controlling such a memory module may include providing a mode register set command from the memory controller to each of the integrated circuit memory devices over the command/address bus during a mode register set operation. A disable signal may be provided from the memory controller to a first one of the integrated circuit memory devices over a signal line between the memory controller and the first integrated circuit memory device to thereby disable implementation of the mode register set command for the first integrated circuit memory device during the mode register set operation.

Abstract: A memory module may include a plurality of memory devices coupled to a memory controller over a same command/address bus. Methods of controlling such a memory module may include providing a mode register set command from the memory controller to each of the integrated circuit memory devices over the command/address bus during a mode register set operation. A disable signal may be provided from the memory controller to a first one of the integrated circuit memory devices over a signal line between the memory controller and the first integrated circuit memory device to thereby disable implementation of the mode register set command for the first integrated circuit memory device during the mode register set operation.