Patents by Inventor Kee-in Bang

Kee-in Bang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8652911
    Abstract: A method of fabricating a semiconductor device includes forming a device isolation region on a semiconductor substrate to define an active region, forming a gate electrode on the active region and the device isolation region across the active region, and forming at least one gate electrode opening portion in the gate electrode so as to overlap an edge portion of the active region, wherein the gate electrode opening portion is simultaneously formed with the gate electrode.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: February 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kee-In Bang, Tae-Jung Lee, Myoung-Kyu Park
  • Patent number: 8143690
    Abstract: Semiconductor device having an on-chip type electrostatic discharge (ESD) protection circuit and a method of manufacturing the same are provided. The on-chip type ESD protection circuit may include a first junction diode having a first conductive type region contacting a second conductive type region in a semiconductor substrate, and a first schottky diode having a metallic material layer arranged on and contacting the first conductive type region of the semiconductor substrate.
    Type: Grant
    Filed: July 21, 2008
    Date of Patent: March 27, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myoung-kyu Park, Byung-sun Kim, Tae-jung Lee, Kee-in Bang
  • Publication number: 20120003805
    Abstract: A method of fabricating a semiconductor device includes forming a device isolation region on a semiconductor substrate to define an active region, forming a gate electrode on the active region and the device isolation region across the active region, and forming at least one gate electrode opening portion in the gate electrode so as to overlap an edge portion of the active region, wherein the gate electrode opening portion is simultaneously formed with the gate electrode.
    Type: Application
    Filed: July 1, 2011
    Publication date: January 5, 2012
    Inventors: Kee-In Bang, Tae-Jung Lee, Myoung-Kyu Park
  • Publication number: 20100123245
    Abstract: A semiconductor integrated circuit device includes: an electrostatic discharge (ESD) impurity region formed in a substrate; a bump formed on the substrate; and a first wiring layer and a second wiring layer formed at the same level under the bump. The first and second wiring layers are separated from each other, and at least part of each of the first and second wiring layers are overlapped by the bump. The first wiring layer is electrically connected to the ESD impurity region and the bump, and the second wiring layer is insulated from the bump.
    Type: Application
    Filed: November 9, 2009
    Publication date: May 20, 2010
    Inventors: Tae-Jung Lee, Kee-In Bang, Myoung-Kyu Park, Kyoung-Eun Uhm
  • Publication number: 20090020844
    Abstract: Semiconductor device having an on-chip type electrostatic discharge (ESD) protection circuit and a method of manufacturing the same are provided. The on-chip type ESD protection circuit may include a first junction diode having a first conductive type region contacting a second conductive type region in a semiconductor substrate, and a first schottky diode having a metallic material layer arranged on and contacting the first conductive type region of the semiconductor substrate.
    Type: Application
    Filed: July 21, 2008
    Publication date: January 22, 2009
    Inventors: Myoung-kyu Park, Byung-sun Kim, Tae-jung Lee, Kee-in Bang