Abstract: A dual band antenna unit for a mobile device may include an antenna receiving part, a first antenna part having a first contact point and a second contact point, a second antenna part, a first feed point and a second feed point. The second antenna part may be formed integrally with the first antenna part and may extend from the first antenna part. The second antenna part may be extractably and retractably mounted in the mobile device. The first antenna part and the second antenna part may have resonant frequencies of different frequency bands. When the second antenna part is extracted, the first contact point may contact the first feed point. When the second antenna part is retracted, the second contact point may contact the second feed point. The mobile device may operate in different frequency bands using a single antenna unit, thereby allowing freedom of internal design and meeting the demand for miniaturization.

Abstract: The present invention relates to an intervertebral disc prosthesis and insertion instrumentation, the prosthesis comprising at least first and second osseous anchoring means, the first osseous anchoring means disposed proximal to the periphery of the plate on which it is situated and the second osseous anchoring means being offset along the antero-posterior axis, the second osseous anchoring means comprising a basal portion and a sharp-edged portion of width narrower than the basal portion. The instrumentation comprises a rod fitted with at least two feet forming a clip and sliding in a tube, sliding the rod in the tube, in the direction of the manipulation end, causing closing of the clip by contact between the exterior of the feet and a truncated portion of the tube and sliding the rod in the tube, in the direction of the prehension end, causing opening of the clip by contact between an axis and the interior of the feet of the rod.

Abstract: The test pattern according to the present invention consists of an opaque metal film pattern formed on a semiconductor substrate, an insulating film formed on the semiconductor substrate and the metal film pattern, a red color filter formed on the insulating film, a planarization layer formed on the insulating film and the red color filter, and a number of micro-lenses formed on the planarization layer.

Abstract: The invention relates to an intervertebral disc prosthesis comprising at least two plates, namely first and second plates, articulated about each other by means of a curved surface, namely articulation, of at least one of the plates, each of the plates comprising a surface known as a contact surface, intended to be in contact with a vertebral plate of one of the vertebrae between which the prosthesis is intended to be inserted, this contact surface for each of the plates comprising a geometrical centre at equal distance from at least two diametrically opposite points located on the periphery of the plate, in which the geometric centres of the plates are not vertically aligned, this off-setting of the geometrical centres of the plates engendering an off-setting of the edges of the plates in at least one direction perpendicular to the vertical axis of the spinal column.

Abstract: The object of this invention is to provide a milling cutter which includes a cutting insert (120), which has a hexahedral shape and is provided with first and second cutting blade parts on opposite ends thereof, and a cutter body (110) provided with a plurality of insert seats (112) which the cutting insert (120) is seated in and fastened to in either of two directions. The cutting insert (120) is fastened to the associated insert seat (112) in a selected direction, thus all corner blades or main blades, provided on the first and second cutting blade parts of the cutting insert, can be used for machining workpieces. Therefore, the present invention extends the lifetime of the cutting insert (120).

Abstract: In one embodiment, an apparatus includes a system circuit adapted to generate at a first output terminal a first output signal in response to a data input signal and at least one system clock signal; a shadow circuit adapted to generate at a second output terminal a second output signal in response the data input signal and the at least one system clock signal; and an output joining circuit coupled to at least the first output terminal and the second output terminal.

Abstract: Dual capacity compressor including a power generating part (20) having a reversible motor (21, 22) and a crank shaft (23) inserted in the motor (21, 23), a compression part (30) having a cylinder (32), a piston (31), and a connecting rod (33), a crank pin (110) in an upper part of the crank shaft (23) eccentric to an axis of the crank shaft, an eccentric sleeve (120) rotatably fitted to the crank pin (110), and the connecting rod (33) respectively, a key member (130) for positive fastening of the eccentric sleeve (120 ) to the crank pin (110) in all rotation directions of the motor, and an eccentric mass (200) provided to the eccentric sleeve (120) for rotating the eccentric sleeve (120) around the crank pin (110), thereby preventing relative motion between components that sustain the eccentricity, and permitting a smooth motion between the components.

Abstract: Circuit responses to a stimulus may be compacted, decreasing the number of pin outs, without increasing the circuit element length, using a compactor. In accordance with one embodiment of the present invention, errors may be detected in scan chains used for integrated circuit testing. The number of outputs applied to output pins or other connectors may be substantially decreased, resulting in cost savings.

Abstract: In one embodiment, an apparatus is provide with a combinational logic circuit to generate a data input signal; a delay element, coupled to the combinational logic circuit, to provide a delayed data input signal in response to the data input signal. Additionally, the apparatus is provided with a system bistable circuit, coupled to the combinational logic circuit, to generate a system bistable signal in response to at least the data input signal; a shadow bistable circuit, coupled to the delay element, to generate a shadow bistable signal in response to at least the delayed data input signal. Further, the apparatus is provided with an output joining circuit, coupled to the system and the shadow bistable circuits, to provide a data output signal in response to the system and the shadow bistable signals.

Abstract: In one embodiment, an apparatus includes a datapath circuit to generate a data output signal in response to a data input signal and at least a first data clock signal; a shadow circuit, coupled to the datapath circuit, to generate a shadow output signal in response the data input signal and at least a second data clock signal during a functional mode of operation and to generate a scan-out signal in response to a scan-in signal and at least a first test clock signal during a test mode of operation; and an error detect circuit, coupled to the datapath and the shadow circuits, to generate an error signal in response to a mismatch between the data output signal and the shadow output signal.

Abstract: A method for forming a contact hole in a semiconductor device is disclosed. The method for forming a contact hole in a semiconductor device comprises depositing a nitride layer and an ILD on a substrate including predetermined devices; forming a first photoresist pattern on the ILD and making a via hole by using the first photoresist pattern; performing a first ashing process; forming a second photoresist pattern on the ILD and making a trench using the second photoresist pattern; conducting a PET; performing a second ashing process and etching the predetermined portion of the nitride layer exposed through the via hole; and wet-cleaning the resulting structure. Accordingly, the present disclosure can fabricate a contact hole maximizing the characteristics of a semiconductor device just by performing a Post Etching Treatment after a trench is formed.

Abstract: A semiconductor device and method for forming the same includes a silicon (111) single crystal substrate, and an epitaxial boron phosphide (BP) layer disposed on the substrate. A group III-nitride semiconductor epitaxial layer is disposed on the BP epitaxial layer.

Abstract: A compactor has a reduced number of outputs and the ability to handle a higher number of errors and unknown logic values. The procedure for designing the matrix and the resulting compactor involves determining the number of unknown logic values that may be encountered and adding columns to the compactor matrix based on the number of errors. Basically, the number of possible combinations of scan in lines is determined. Then, additional columns are added for each possible combination of scan in lines. The number of columns that are added for each combination of scan in lines is equal to the number of errors plus one in one embodiment.

Abstract: An analog buffer for buffering an input voltage to an output line is provided. The analog buffer includes a constant current source and a comparator. The constant current source supplies a constant current to the output line, and the comparator compares a voltage charged on the output line with the input voltage to turn-off the constant current source if it is determined that the voltage charged on the output line corresponding to the input voltage is buffered to the output line.

Abstract: An analog buffer circuit for a liquid crystal display (LCD) device includes a first capacitor and an inverter connected in series between an input terminal and an output terminal, a first reset switch connected between the input terminal and the first capacitor to reset the first capacitor, a first feedback switch connected to a first node between the first capacitor and the first reset switch, a second capacitor and a second feedback switch connected in series between a second node and a third node, the second node connected between the first capacitor and the inverter, and the third node connected between the inverter and the output terminal, a second reset switch connected between the second node and the third node to reset the inverter, and a third reset switch connected to a fourth node between the second capacitor and the second feedback switch to reset the second capacitor.

Abstract: A gate valve mechanism is provided which is especially designed for use as a hot tap valve. The valve incorporates a fabricated valve body having internal seat rings with circular elastomer sealing elements disposed within circular sealed grooves formed therein. A slab gate member is movable between the seat members between open and closed positions and is positionable radially outwardly of the seal grooves to permit replacement of the elastomer seal members. The valve body structure is of minimal thickness to permit access to the seal members through the flow ports of the valve in order to permit seal replacement. The valve also incorporates an internal rotatable threaded drive stem which receives a drive nut interconnected with the gate to thus permit opening and closing movement of the gate member by simply rotating the valve stem.