Abstract: The invention discloses a package structure including a semiconductor device, a first protection layer, a second protection layer and at least one conductive connector. The semiconductor device has at least one pad. The first protection layer is disposed on the semiconductor device and exposes the pad. The second protection layer, disposed on the first protection layer, has at least one first opening and at least one second opening. The first opening exposes a partial surface of the pad. The second opening exposes a partial surface of the first protection layer. The conductive connector, opposite to the pad, is disposed on the second protection layer and coupled to the pad through the first openings.

Abstract: A chip level package utilizing a CGA is described. A semiconductor chip with pillars is molded in an encapsulant. Solder balls are added and connected to the chip pillars. The final package does not require a first level substrate or interposer and is able to be assembled to the next level as is. An additional embodiment describes the addition of a thermal heat sink to the packaged chip.

Abstract: A method for forming semiconductor packages is disclosed. The method involves providing a support substrate and forming at least one conductive layer thereon. The method also includes coupling the at least one conductive layer to a support face of a film substrate for securing the at least one conductive layer to the support face and removing the support substrate from the at least one conductive layer. The at least one interconnector is adhered to the film substrate for forming an interposer. The method further involves bonding a integrated circuit chip to the at least one conductive layer of the interposer and disposing a compound over the support face to thereby encapsulate the integrated circuit chip and the least one conductive layer for forming an encapsulated package therefrom. Portions of the at least one conductive layer is then exposed by removing the film substrate from the encapsulated package.

Abstract: As the functionality, speed and portability of consumer electronics increases, so does the need for more circuitry to be packed into smaller spaces. All this leads to the fact that the size of a device is now becoming more often a function of the circuit board or module size than anything else. In order to achieve size reduction of multi-featured products, passive components on the surface of the circuit need to be eliminated by burying them within the inner layers of the printed wiring board. Embedded passives are passive components placed between the interconnecting substrates of a printed wiring board. Implementation of embedded passives reduces space requirements and enables more silicon devices to be placed on the same sized substrate, thereby allowing functional potential of small electronic devices to increase. However, additional steps are conventionally required for embedding passive components within the interconnect layer between substrates.

Abstract: A chip level package utilizing a CGA is described. A semiconductor chip with pillars is molded in an encapsulant. Solder balls are added and connected to the chip pillars. The final package does not require a first level substrate or interposer and is able to be assembled to the next level as is. An additional embodiment describes the addition of a thermal heat sink to the packaged chip.

Abstract: A semiconductor chip packaging structure is described. The structure comprising of a semiconductor chip interconnected to a recessed lead frame and the resultant assembly encapsulated in a molding compound. The final product is a reverse mounted semiconductor chip in a leadless quad flat pack configuration. A second embodiment allows for the semiconductor chip backside to be exposed for thermal enhancements. Manufacturing methods are also described for the two embodiments disclosed.

Abstract: A chip level package utilizing a CGA is described. A semiconductor chip with pillars is molded in an encapsulant. Solder balls are added and connected to the chip pillars. The final package does not require a first level substrate or interposer and is able to be assembled to the next level as is.

Abstract: A method and structure for controlling solder spread in a predefined/designed area during flip chip assembly build is disclosed. Using conventional processes used in the art blind holes or dimples are incorporated onto the lead frame which then act as containers or wells trapping the solder and thereby preventing it from spreading wider.

Abstract: A chip level package utilizing a CGA is described. A semiconductor chip with pillars is molded in an encapsulant. Solder balls are added and connected to the chip pillars. The final package does not require a first level substrate or interposer and is able to be assembled to the next level as is.

Abstract: A chip level package utilizing a CGA is described. A semiconductor chip with pillars is molded in an encapsulant. Solder balls are added and connected to the chip pillars. The final package does not require a first level substrate or interposer and is able to be assembled to the next level as is. An additional embodiment describes the addition of a thermal heat sink to the packaged chip.