Patents by Inventor Kee-sik Ahn
Kee-sik Ahn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240071540Abstract: Various embodiments of the present disclosure relate to a non-volatile memory device including a sense amplifier and an operation method thereof. The non-volatile memory device may include: a memory cell array comprising a plurality of memory cells; and the sense amplifier configured to read data of the plurality of memory cells and output the read data. The sense amplifier may include: a first stage sense amplifier configured to sense a voltage difference between a reference voltage and a voltage of a bit line connected to at least one memory cell among the plurality of memory cells, and perform a primary amplification of the sensed voltage difference; and a second stage sense amplifier configured to perform a secondary amplification of a first result of the primary amplification and output a second result of the secondary amplification.Type: ApplicationFiled: November 6, 2023Publication date: February 29, 2024Applicant: KEY FOUNDRY CO., LTD.Inventors: Seong Jun PARK, Sung Bum PARK, Kee Sik AHN
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Patent number: 11915767Abstract: A negative voltage switching device includes a first switching circuit configured to transmit a first negative voltage, a second switching circuit configured to transmit a second negative voltage, and a switching selection circuit configured to select one of the first switching circuit or the second switching circuit for transmitting one of the first negative voltage and the second negative voltage to an output terminal.Type: GrantFiled: January 4, 2022Date of Patent: February 27, 2024Assignee: KEY FOUNDRY CO., LTD.Inventors: Jin Hyung Kim, Sung Bum Park, Kee Sik Ahn
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Publication number: 20240046992Abstract: An eFuse cell is provided. The eFuse cell may include a first PMOS transistor and a first NMOS transistor configured to receive a programmed state selection (BLOWB) signal, a second PMOS transistor and a second NMOS transistor configured to receive a write word line bar (WWLB) for a program operation, a first read NMOS transistor and a second read NMOS transistor configured to receive a read word line (RWL) for a read operation, a program transistor configured to control a program current to flow for a fusing operation, and an eFuse connected between the first read NMOS transistor and the second read NMOS transistor.Type: ApplicationFiled: October 6, 2023Publication date: February 8, 2024Applicant: KEY FOUNDRY CO., LTD.Inventors: Seong Jun PARK, Jong Min CHO, Sung Bum PARK, Kee Sik AHN
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Patent number: 11854622Abstract: An eFuse cell is provided. The eFuse cell may include a first PMOS transistor and a first NMOS transistor configured to receive a programmed state selection (BLOWB) signal, a second PMOS transistor and a second NMOS transistor configured to receive a write word line bar (WWLB) for a program operation, a first read NMOS transistor and a second read NMOS transistor configured to receive a read word line (RWL) for a read operation, a program transistor configured to control a program current to flow for a fusing operation, and an eFuse connected between the first read NMOS transistor and the second read NMOS transistor.Type: GrantFiled: November 30, 2021Date of Patent: December 26, 2023Assignee: KEY FOUNDRY CO., LTD.Inventors: Seong Jun Park, Jong Min Cho, Sung Bum Park, Kee Sik Ahn
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Patent number: 11848061Abstract: Various embodiments of the present disclosure relate to a non-volatile memory device including a sense amplifier and an operation method thereof. The non-volatile memory device may include: a memory cell array comprising a plurality of memory cells; and the sense amplifier configured to read data of the plurality of memory cells and output the read data. The sense amplifier may include: a first stage sense amplifier configured to sense a voltage difference between a reference voltage and a voltage of a bit line connected to at least one memory cell among the plurality of memory cells, and perform a primary amplification of the sensed voltage difference; and a second stage sense amplifier configured to perform a secondary amplification of a first result of the primary amplification and output a second result of the secondary amplification.Type: GrantFiled: May 11, 2022Date of Patent: December 19, 2023Assignee: KEY FOUNDRY CO., LTD.Inventors: Seong Jun Park, Sung Bum Park, Kee Sik Ahn
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Publication number: 20230238069Abstract: Various embodiments of the present disclosure relate to a non-volatile memory device including a sense amplifier and an operation method thereof. The non-volatile memory device may include: a memory cell array comprising a plurality of memory cells; and the sense amplifier configured to read data of the plurality of memory cells and output the read data. The sense amplifier may include: a first stage sense amplifier configured to sense a voltage difference between a reference voltage and a voltage of a bit line connected to at least one memory cell among the plurality of memory cells, and perform a primary amplification of the sensed voltage difference; and a second stage sense amplifier configured to perform a secondary amplification of a first result of the primary amplification and output a second result of the secondary amplification.Type: ApplicationFiled: May 11, 2022Publication date: July 27, 2023Applicant: KEY FOUNDRY CO., LTD.Inventors: Seong Jun PARK, Sung Bum PARK, Kee Sik AHN
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Publication number: 20230107619Abstract: A non-volatile memory device includes a first fuse cell array and a second fuse cell array, spaced from each other; a first ground ring region and a second ground ring region disposed to surround the first fuse cell array and the second fuse cell array, respectively; a third ground ring region configured to connect the first ground ring region and the second ground ring region; a power ring region disposed to surround the first ground ring region and the second ground ring region; and an address decoder, disposed between the first fuse cell array and the second fuse cell array, configured to supply a word line signal to each of the first fuse cell array and the second fuse cell array. The ground ring regions supply a ground voltage to each of the first fuse cell array and the second fuse cell array.Type: ApplicationFiled: March 14, 2022Publication date: April 6, 2023Applicant: KEY FOUNDRY CO., LTD.Inventors: Seong Jun PARK, Jong Min CHO, Sung Bum PARK, Kee Sik AHN
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Publication number: 20230087413Abstract: An octo mode program and erase operation method to reduce test time in a non-volatile memory device. M/8 word lines corresponding to an octo row, among M word lines, are simultaneously selected, and a write voltage is applied to memory cells connected to M/8 word lines corresponding to the octo row. A voltage that is different from the write voltage is applied to memory cells connected to the rest of word lines, except for M/8 word lines corresponding to the octo row, when the octo signal is applied to an address decoder.Type: ApplicationFiled: November 30, 2021Publication date: March 23, 2023Applicant: KEY FOUNDRY CO., LTD.Inventors: Weon-Hwa JEONG, Young Chul SEO, Chul Geun LIM, Yong Hwan KIM, Sung Bum PARK, Kee Sik AHN
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Publication number: 20230070554Abstract: A multi time program device with a power switch and a non-volatile memory implementing the power switch for multi time program is provided. The device performs a program operation or an erase operation of a non-volatile memory cell in a non-volatile memory device.Type: ApplicationFiled: December 7, 2021Publication date: March 9, 2023Applicant: KEY FOUNDRY CO., LTD.Inventors: Jin Hyung KIM, Sung Bum PARK, Kee Sik AHN
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Publication number: 20230065879Abstract: A negative voltage switching device includes a first switching circuit configured to transmit a first negative voltage, a second switching circuit configured to transmit a second negative voltage, and a switching selection circuit configured to select one of the first switching circuit or the second switching circuit for transmitting one of the first negative voltage and the second negative voltage to an output terminalType: ApplicationFiled: January 4, 2022Publication date: March 2, 2023Applicant: KEY FOUNDRY CO., LTD.Inventors: Jin Hyung KIM, Sung Bum PARK, Kee Sik AHN
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Publication number: 20230048824Abstract: An eFuse cell is provided. The eFuse cell may include a first PMOS transistor and a first NMOS transistor configured to receive a programmed state selection (BLOWB) signal, a second PMOS transistor and a second NMOS transistor configured to receive a write word line bar (WWLB) for a program operation, a first read NMOS transistor and a second read NMOS transistor configured to receive a read word line (RWL) for a read operation, a program transistor configured to control a program current to flow for a fusing operation, and an eFuse connected between the first read NMOS transistor and the second read NMOS transistor.Type: ApplicationFiled: November 30, 2021Publication date: February 16, 2023Applicant: KEY FOUNDRY CO., LTD.Inventors: Seong Jun PARK, Jong Min CHO, Sung Bum PARK, Kee Sik AHN
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Patent number: 11538541Abstract: A semiconductor device includes a first word line configured to perform a writing operation or a programing operation, a second word line configured to perform a read operation, a first switching device including a first gate electrode and a first node, a second switching device comprising a second gate electrode and a second node, an electrical fuse (e-fuse) disposed between the first node and the second node, and a diode coupled to the first node and the first word line, wherein the first gate electrode and the second gate electrode are coupled to the second word line.Type: GrantFiled: March 14, 2022Date of Patent: December 27, 2022Assignee: KEY FOUNDRY CO., LTD.Inventors: Jong Min Cho, Sung Bum Park, Kee Sik Ahn, Seong Jun Park
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Publication number: 20220199177Abstract: A semiconductor device includes a first word line configured to perform a writing operation or a programing operation, a second word line configured to perform a read operation, a first switching device including a first gate electrode and a first node, a second switching device comprising a second gate electrode and a second node, an electrical fuse (e-fuse) disposed between the first node and the second node, and a diode coupled to the first node and the first word line, wherein the first gate electrode and the second gate electrode are coupled to the second word line.Type: ApplicationFiled: March 14, 2022Publication date: June 23, 2022Applicant: KEY FOUNDRY CO., LTD.Inventors: Jong Min CHO, Sung Bum PARK, Kee Sik AHN, Seong Jun PARK
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Patent number: 11328783Abstract: A semiconductor device includes a first word line configured to perform a writing operation or a programing operation, a second word line configured to perform a read operation, a first switching device including a first gate electrode and a first node, a second switching device comprising a second gate electrode and a second node, an electrical fuse (e-fuse) disposed between the first node and the second node, and a diode coupled to the first node and the first word line, wherein the first gate electrode and the second gate electrode are coupled to the second word line.Type: GrantFiled: April 22, 2021Date of Patent: May 10, 2022Assignee: KEY FOUNDRY CO., LTD.Inventors: Jong Min Cho, Sung Bum Park, Kee Sik Ahn, Seong Jun Park
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Patent number: 11145379Abstract: An eFuse cell array includes a first unit cell and a second unit cell, each including a PN diode, a cell read transistor, and a fuse element. A first placement order of the PN diode, the cell read transistor, and the fuse element in the first unit cell is reversed with respect to a second placement order of the PN diode, the cell read transistor, and the fuse element in the second unit cell.Type: GrantFiled: August 14, 2020Date of Patent: October 12, 2021Assignee: Key Foundry Co., Ltd.Inventors: Jong Min Cho, Sung Bum Park, Kee Sik Ahn, Seong Jun Park
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Publication number: 20210241841Abstract: A semiconductor device includes a first word line configured to perform a writing operation or a programing operation, a second word line configured to perform a read operation, a first switching device including a first gate electrode and a first node, a second switching device comprising a second gate electrode and a second node, an electrical fuse (e-fuse) disposed between the first node and the second node, and a diode coupled to the first node and the first word line, wherein the first gate electrode and the second gate electrode are coupled to the second word line.Type: ApplicationFiled: April 22, 2021Publication date: August 5, 2021Applicant: KEY FOUNDRY CO., LTD.Inventors: Jong Min CHO, Sung Bum PARK, Kee Sik AHN, Seong Jun PARK
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Patent number: 11024398Abstract: A semiconductor device includes a first word line configured to perform a writing operation or a programing operation, a second word line configured to perform a read operation, a first switching device including a first gate electrode and a first node, a second switching device comprising a second gate electrode and a second node, an electrical fuse (e-fuse) disposed between the first node and the second node, and a diode coupled to the first node and the first word line, wherein the first gate electrode and the second gate electrode are coupled to the second word line.Type: GrantFiled: April 15, 2020Date of Patent: June 1, 2021Assignee: KEY FOUNDRY CO., LTD.Inventors: Jong Min Cho, Sung Bum Park, Kee Sik Ahn, Seong Jun Park
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Publication number: 20210125677Abstract: A semiconductor device includes a first word line configured to perform a writing operation or a programing operation, a second word line configured to perform a read operation, a first switching device including a first gate electrode and a first node, a second switching device comprising a second gate electrode and a second node, an electrical fuse (e-fuse) disposed between the first node and the second node, and a diode coupled to the first node and the first word line, wherein the first gate electrode and the second gate electrode are coupled to the second word line.Type: ApplicationFiled: April 15, 2020Publication date: April 29, 2021Applicant: KEY FOUNDRY CO., LTD.Inventors: Jong Min CHO, Sung Bum PARK, Kee Sik AHN, Seong Jun PARK
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Publication number: 20210125678Abstract: An eFuse cell array includes a first unit cell and a second unit cell, each including a PN diode, a cell read transistor, and a fuse element. A first placement order of the PN diode, the cell read transistor, and the fuse element in the first unit cell is reversed with respect to a second placement order of the PN diode, the cell read transistor, and the fuse element in the second unit cell.Type: ApplicationFiled: August 14, 2020Publication date: April 29, 2021Applicant: KEY FOUNDRY CO., LTD.Inventors: Jong Min CHO, Sung Bum PARK, Kee Sik AHN, Seong Jun PARK
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Patent number: 10008508Abstract: A non-volatile semiconductor storage device includes a gate insulating film formed on a semiconductor substrate, a gate electrode formed on the gate insulating film, and first and second spaced apart doped regions formed below the gate insulating film and the gate electrode in the semiconductor substrate, wherein a grounded region of the first and second spaced apart doped regions is grounded via a contact.Type: GrantFiled: April 24, 2017Date of Patent: June 26, 2018Assignee: Magnachip Semiconductor, Ltd.Inventors: Duk Ju Jeong, Sung Bum Park, Kee Sik Ahn, Young Chul Seo