Patents by Inventor Keeho Kim

Keeho Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240192609
    Abstract: An OPC modeling method is disclosed, which includes: step S1: determining optical model parameters and resist model parameters; step S2: obtaining a plurality of parameter combinations by stochastically choosing values for the parameters; step S3: performing photolithography simulations and etching wafers and calculating RMS values of differences between simulated CDs and etching CDs and BCE values of the CDs; step S4: evaluating the values according to Pareto principle and calculating Pareto optimum to N-th-best Pareto suboptimum sets to prioritize the plurality of parameter combinations in a descending order; step S5: applying a genetic algorithm with position-based crossover and/or mutation to the plurality of parameter combinations, to obtain new parameter combinations; and step S6: iterating steps S3 to S5 on the new parameter combinations until a number of iterations reaches a first predetermined value and using highest prioritized ones of parameter combinations resulting from a last iteration for OPC m
    Type: Application
    Filed: December 7, 2022
    Publication date: June 13, 2024
    Inventors: Yinuo PAN, Yingfang WANG, Keeho KIM, Norman S. CHEN, Eric S. PARENT
  • Patent number: 6866974
    Abstract: A method of providing critical dimension (CD) gate control during photolithography is achieved by scanning a trial wafer from a batch by an exposure tool and then measuring the gate width to determine shot zones for bi-shot (BSE) exposure. The time delay based on shot or exposure order is determined for each BSE zone. The shot or exposure dose for the other wafers from the same or similar batch is then determined on the bi-shot exposure and the shot order.
    Type: Grant
    Filed: October 21, 2002
    Date of Patent: March 15, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Keeho Kim, Jarvis B. Jacobs, Reima T. Laaksonen
  • Publication number: 20040076896
    Abstract: A method of providing critical dimension (CD) gate control during photolithography is achieved by scanning a trial wafer from a batch by an exposure tool and then measuring the gate width to determine shot zones for bi-shot (BSE) exposure. The time delay based on shot or exposure order is determined for each BSE zone. The shot or exposure dose for the other wafers from the same or similar batch is then determined on the bi-shot exposure and the shot order.
    Type: Application
    Filed: October 21, 2002
    Publication date: April 22, 2004
    Inventors: Keeho Kim, Jarvis B. Jacobs, Reima T. Laaksonen