Patents by Inventor Keeho Kim

Keeho Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor process using delay-compensated exposure
    Patent number: 6866974
    Abstract: A method of providing critical dimension (CD) gate control during photolithography is achieved by scanning a trial wafer from a batch by an exposure tool and then measuring the gate width to determine shot zones for bi-shot (BSE) exposure. The time delay based on shot or exposure order is determined for each BSE zone. The shot or exposure dose for the other wafers from the same or similar batch is then determined on the bi-shot exposure and the shot order.
    Type: Grant
    Filed: October 21, 2002
    Date of Patent: March 15, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Keeho Kim, Jarvis B. Jacobs, Reima T. Laaksonen
  • Semiconductor process using delay-compensated exposure
    Publication number: 20040076896
    Abstract: A method of providing critical dimension (CD) gate control during photolithography is achieved by scanning a trial wafer from a batch by an exposure tool and then measuring the gate width to determine shot zones for bi-shot (BSE) exposure. The time delay based on shot or exposure order is determined for each BSE zone. The shot or exposure dose for the other wafers from the same or similar batch is then determined on the bi-shot exposure and the shot order.
    Type: Application
    Filed: October 21, 2002
    Publication date: April 22, 2004
    Inventors: Keeho Kim, Jarvis B. Jacobs, Reima T. Laaksonen