Abstract: A memory system is deigned for impedance matching using a network of resistors that are tuned to reduce reflections on a shared bus. Any deviation from the matched state causes a mismatch and results in reflections on the bus. Overall signal reflections are reduced by balancing the back reflections occurring at a connector junction coupled to a pair of resistors and the back reflections occurring at the input of the DIMMs. This balance or tradeoff is achieved by changing the resistance value of the resistor pair to reduce the overall back reflections in the memory system.

Abstract: A server including a cooling fan assembly and an input/output assembly at opposite ends of the server, and a processor assembly located between the cooling fan assembly and input/output assembly. The server also includes a cover plate that covers the processor assembly and cooling fan assembly and that has a power supply on the face of the cover plate facing the processor assembly and is electrically connected to the processor assembly.

Abstract: A server including a cooling fan assembly and an input/output assembly at opposite ends of the server, and a processor assembly located between the cooling fan assembly and input/output assembly. The server also includes a cover plate that covers the processor assembly and cooling fan assembly and that has a power supply on the face of the cover plate facing the processor assembly and is electrically connected to the processor assembly.

Abstract: A processor card for supporting multiple cache configurations, and a microprocessor for selecting one of the multiple cache configurations is disclosed. The processor card has a first static random access memory mounted on a front side thereof and a second static random access memory mounted on a rear side thereof. The address pins of the memories are aligned. Each pair of aligned address pins are electrically coupled to thereby concurrently receive an address bit signal from the microprocessor. During an initial boot of the microprocessor, the microprocessor includes a multiplexor for providing the address bit signals to the address pins in response to a control signal indicative of a selected cache configuration.

Abstract: A processor card for supporting multiple cache configurations, and a microprocessor for selecting one of the multiple cache configurations is disclosed. The processor card has a first static random access memory mounted on a front side thereof and a second static random access memory mounted on a rear side thereof. The address pins of the memories are aligned. Each pair of aligned address pins are electrically coupled to thereby concurrently receive an address bit signal from the microprocessor. During an initial boot of the microprocessor, the microprocessor includes a multiplexor for providing the address bit signals to the address pins in response to a control signal indicative of a selected cache configuration.

Abstract: A processor card for supporting multiple cache configurations, and a microprocessor for selecting one of the multiple cache configurations is disclosed. The processor card has a first static random access memory mounted on a front side thereof and a second static random access memory mounted on a rear side thereof. The address pins of the memories are aligned. Each pair of aligned address pins are electrically coupled to thereby concurrently receive an address bit signal from the microprocessor. During an initial boot of the microprocessor, the microprocessor includes a multiplexor for providing the address bit signals to the address pins in response to a control signal indicative of a selected cache configuration.

Abstract: A processor card for supporting multiple cache configurations, and a microprocessor for selecting one of the multiple cache configurations is disclosed. The processor card has a first static random access memory mounted on a front side thereof and a second static random access memory mounted on a rear side thereof. The address pins of the memories are aligned. Each pair of aligned address pins are electrically coupled to thereby concurrently receive an address bit signal from the microprocessor. During an initial boot of the microprocessor, the microprocessor includes a multiplexor for providing the address bit signals to the address pins in response to a control signal indicative of a selected cache configuration.