Patents by Inventor Keeshik PARK

Keeshik PARK has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory device having buried gate and method of fabricating the same
    Patent number: 9691769
    Abstract: A memory device includes a substrate including active areas and isolation areas, trenches in the isolation areas, active patterns in the active areas, the active patterns protruding from the substrate, isolation layers filling the trenches, gate trenches crossing the active patterns and the isolation layers, and gate line stacks filling the gate trenches, a first width of the gate trench in the isolation layer being greater than a second width of the gate trench in the active pattern.
    Type: Grant
    Filed: July 28, 2015
    Date of Patent: June 27, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yongjun Kim, Keeshik Park, Jungwoo Song, Sang-Jun Lee, Donggyun Han, Jaerok Kahng
  • MEMORY DEVICE HAVING BURIED GATE AND METHOD OF FABRICATING THE SAME
    Publication number: 20160149008
    Abstract: A memory device includes a substrate including active areas and isolation areas, trenches in the isolation areas, active patterns in the active areas, the active patterns protruding from the substrate, isolation layers filling the trenches, gate trenches crossing the active patterns and the isolation layers, and gate line stacks filling the gate trenches, a first width of the gate trench in the isolation layer being greater than a second width of the gate trench in the active pattern.
    Type: Application
    Filed: July 28, 2015
    Publication date: May 26, 2016
    Inventors: Yongjun KIM, Keeshik PARK, Jungwoo SONG, Sang-Jun LEE, Donggyun HAN, Jaerok KAHNG
  • Semiconductor devices and dynamic random access memory devices including buried gate pattern with high-k capping layer
    Patent number: 8610191
    Abstract: Semiconductor devices and dynamic random access memory devices including a buried gate electrode are provided, the semiconductor devices include a substrate with a gate trench, a buried gate electrode partially filling the inside of the gate trench, a capping layer pattern in the gate trench and over the buried gate electrode, source/drain regions below an upper surface of the substrate and adjacent to both sides of the buried gate electrode, and a gate insulation layer interposed between the trench and the buried gate electrode. The capping layer pattern includes a high-k material layer that directly contacts an upper surface of the buried gate electrode.
    Type: Grant
    Filed: December 2, 2010
    Date of Patent: December 17, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joon-Seok Moon, Dong-Soo Woo, Jaerok Kahng, Jinwoo Lee, Keeshik Park
  • SEMICONDUCTOR DEVICES AND DYNAMIC RANDOM ACCESS MEMORY DEVICES INCLUDING BURIED GATE PATTERN WITH HIGH-K CAPPING LAYER
    Publication number: 20110169066
    Abstract: Semiconductor devices and dynamic random access memory devices including a buried gate electrode are provided, the semiconductor devices include a substrate with a gate trench, a buried gate electrode partially filling the inside of the gate trench, a capping layer pattern in the gate trench and over the buried gate electrode, source/drain regions below an upper surface of the substrate and adjacent to both sides of the buried gate electrode, and a gate insulation layer interposed between the trench and the buried gate electrode. The capping layer pattern includes a high-k material layer that directly contacts an upper surface of the buried gate electrode.
    Type: Application
    Filed: December 2, 2010
    Publication date: July 14, 2011
    Inventors: Joon-Seok MOON, Dong-Soo WOO, Jaerok KAHNG, Jinwoo LEE, Keeshik PARK