Abstract: An apparatus is provided which comprises at least one processor, at least one memory including computer program code, and the at least one processor, with the at least one memory and the computer program code, being arranged to cause the apparatus to at least perform generating a code block including information bits and parity bits, the parity bits being generated by performing a cyclic redundancy check on the information bits, determining the number of parity bits used in generating the code block based on an applied linear error correcting code base graph and/or based on the number of the information bits, and encoding the code block by using the applied linear error correcting code base graph.

Abstract: This document discloses a solution for error detection. According to an aspect, a method comprises: generating, by a first apparatus, a transport block and error detection bits for the transport block; generating, by the first apparatus, a first number of code block groups by using the transport block and the error detection bits, wherein the first number is two or higher and based on a number of code blocks a second apparatus is able to decode in parallel processing; generating, by the first apparatus, error detection bits for at least one of the code block groups; generating, by the first apparatus, a plurality of code blocks for each code block group, and causing transmission of the plurality of code blocks to the second apparatus.

Abstract: A method for encoding a sequence of control information bits comprising: generating a sequence of error detection bits based on the sequence of control information bits; generating a sequence of error correction bits based on the sequence of control information bits; and distributing the sequence of error detection bits and the sequence of error correction bits between the sequence of control information bits to form a combined sequence of bits, such that the bit order of the combined sequence of bits following the distribution enables an error detection check to be performed before or after a first error correction check bit.

Abstract: A base matrix is applied to an LDPC coder. The base matrix includes multiple parts, each including multiple of rows and columns, and containing integers, each representative of an identity matrix cyclically shifted in accordance with the integer or representative of an all-zero matrix. At least two of the multiple parts are configured such that their respective column-wise combinations of rows represents a same starting vector, cyclically shifted or interleaved, with zero or more but not all integers not indicative of the all-zero matrix of the same vector substituted by integers indicative of the all-zero matrix. The at least two of the multiple parts are not identical. The applied base matrix is used for one of encoding data using the LDPC coder or decoding data using the LDPC coder.

Abstract: Redundancy information is added to information to be sent over a medium and sent as spatially coupled chain with the redundancy information as local decision verification codes. In the receiving end, when the local decision verification code has been satisfied a preset number of times, a sliding window is shifted.

Abstract: A method includes accessing information, and at least one of encoding or decoding the information using a parity check matrix based on a coding rate. A portion of a data part in the parity check matrix has been generated based on part or all of another matrix. Apparatus, computer programs, and computer program products are also described. The apparatus may be a wireless mobile device or a wireless network access node. A communication system may include one or more of the wireless mobile devices and one or more of the access nodes, each using a version of the method.

Abstract: This document discloses a solution for error detection. According to an aspect, a method comprises: generating, by a first apparatus, a transport block and error detection bits for the transport block; generating, by the first apparatus, a first number of code block groups by using the transport block and the error detection bits, wherein the first number is two or higher and based on a number of code blocks a second apparatus is able to decode in parallel processing; generating, by the first apparatus, error detection bits for at least one of the code block groups; generating, by the first apparatus, a plurality of code blocks for each code block group, and causing transmission of the plurality of code blocks to the second apparatus.

Abstract: A base matrix is applied to an LDPC coder. The base matrix includes multiple parts, each including multiple of rows and columns, and containing integers, each representative of an identity matrix cyclically shifted in accordance with the integer or representative of an all-zero matrix. At least two of the multiple parts are configured such that their respective column-wise combinations of rows represents a same starting vector, cyclically shifted or interleaved, with zero or more but not all integers not indicative of the all-zero matrix of the same vector substituted by integers indicative of the all-zero matrix. The at least two of the multiple parts are not identical. The applied base matrix is used for one of encoding data using the LDPC coder or decoding data using the LDPC coder.

Abstract: An apparatus is provided which comprises at least one processor, at least one memory including computer program code, and the at least one processor, with the at least one memory and the computer program code, being arranged to cause the apparatus to at least perform generating a code block including information bits and parity bits, the parity bits being generated by performing a cyclic redundancy check on the information bits, determining the number of parity bits used in generating the code block based on an applied linear error correcting code base graph and/or based on the number of the information bits, and encoding the code block by using the applied linear error correcting code base graph.

Abstract: A method including determining a cyclic redundancy check (CRC) generator sequence defining a one to one mapping between a sequence of control information values and cyclic redundancy check (CRC) sequence values; and determining a combined sequence, the combined sequence formed by distributing the cyclic redundancy check (CRC) value sequence within the sequence of control information values, wherein the distributing the cyclic redundancy check (CRC) value sequence within the sequence of control information values is based on a selected part of the cyclic redundancy check (CRC) generator sequence.

Abstract: Polar Codes for Downlink Control Channels for Wireless Networks A technique is provided for decoding downlink control information that was encoded using polar encoding, the technique including: attempting, based on an initial assumption by a user device of a segmented downlink control information, to decode a first codeword provided via a user device-specific resource, the first codeword including a first downlink control information segment and a pointer to a second downlink control information segment of a segmented downlink control information; decoding, if the attempting to decode is successful, based on the pointer, a second codeword that includes the second downlink control information segment of the segmented downlink control information; and otherwise, if the attempting to decode is unsuccessful, making an assumption of a non-segmented downlink control information and decoding a third codeword to obtain a non-segmented downlink control information.

Abstract: Identification of communication participants may be an important aspect of various communication systems. For example, fifth generation (5G) wireless communication systems may benefit from suitable recipient identification. A method can include obtaining data bits to be communicated to a target device. The method can also include obtaining identification bits corresponding to at least one of sender or receiver of the data bits. The method can further include multiplexing the data bits with the identification bits.

Abstract: A method includes accessing information, and at least one of encoding or decoding the information using a parity check matrix based on a coding rate. A portion of a data part in the parity check matrix has been generated based on part or all of another matrix. Apparatus, computer programs, and computer program products are also described. The apparatus may be a wireless mobile device or a wireless network access node. A communication system may include one or more of the wireless mobile devices and one or more of the access nodes, each using a version of the method.

Abstract: Various communication systems may benefit from efficient encoding and decoding. For example, certain multiple-input multiple-output devices may benefit from efficient encoding and decoding while operating with two codewords. A method can include receiving a first codeword and a second codeword. The method can also include segmenting the first codeword and the second codeword to provide similar sub-matrix dimensions. The method can further include outputting similarly sub-matrix dimensioned code blocks of the first codeword and the second codeword as a first code blocks and second code blocks.