Abstract: A memory array that includes a plurality of storage cells, a plurality of bit lines, a plurality of memory transistor word lines and a plurality of selection transistor word lines, wherein the storage cells form an array of M rows*N columns; each storage cell includes a selection transistor and a memory transistor connected in series; a source and a gate of each selection transistor are connected, and the gates of the selection transistors in the same row are connected to a corresponding selection transistor word line.

Abstract: An embedded SONOS memory and a method for making the same. The method includes: forming a connecting layer on one side of a selection transistor polysilicon gate; forming a second silicon oxide layer and an ONO charge storage layer on the other side of the selection transistor polysilicon gate far away from the connecting layer; then forming a memory transistor polysilicon gate on the side of the second silicon oxide layer far away from the connecting layer, so as to obtain the selection transistor polysilicon gate and the memory transistor polysilicon gate in a back-to-back structure.

Abstract: A memory array that includes a plurality of storage cells, a plurality of bit lines, a plurality of memory transistor word lines and a plurality of selection transistor word lines, wherein the storage cells form an array of M rows*N columns; each storage cell includes a selection transistor and a memory transistor connected in series; a source and a gate of each selection transistor are connected, and the gates of the selection transistors in the same row are connected to a corresponding selection transistor word line.

Abstract: A SONOS nonvolatile memory includes a second gate structure of a selectron isolated from a first gate structure of a memotron by an inter-gate dielectric isolation layer formed on a first side of the first gate structure through self-alignment. The second gate structure is formed on a first side of the inter-gate dielectric isolation layer through self-alignment. A cell structure is formed by two adjacent cell structures. A first window defines an area formed by the two first gate structures. Two sides of each first gate structure are defined through self-alignment by first top silicon nitride layers formed on inner sides of the first window. First silicon nitride spacers are formed on second sides of the first gate structures through self-alignment. The bottom area of a contact hole between the second sides of the first gate structures is defined through self-alignment by the two first silicon nitride spacers.

Abstract: A SONOS nonvolatile memory includes a second gate structure of a selectron isolated from a first gate structure of a memotron by an inter-gate dielectric isolation layer formed on a first side of the first gate structure through self-alignment. The second gate structure is formed on a first side of the inter-gate dielectric isolation layer through self-alignment. A cell structure is formed by two adjacent cell structures. A first window defines an area formed by the two first gate structures. Two sides of each first gate structure are defined through self-alignment by first top silicon nitride layers formed on inner sides of the first window. First silicon nitride spacers are formed on second sides of the first gate structures through self-alignment. The bottom area of a contact hole between the second sides of the first gate structures is defined through self-alignment by the two first silicon nitride spacers.

Abstract: A method for preventing wafer edge peeling in a metal wiring process. A buffer layer is formed between a diffusion barrier layer of a metal wiring substructure and a semiconductor substrate. The buffer layer is an insulating dielectric layer, preferably a silicon oxide layer, or a polysilicon layer. The silicon oxide layer is formed in a process for forming a Shallow Trench Isolation (STI) structure. Using the above processes, the structure of direct contact between the diffusion barrier layer of the metal wiring structure and the semiconductor substrate can be avoided, and hence wafer edge peeling can be avoided without any modification to a conventional semiconductor fabrication procedure and with low cost and improved operability. This method is applicable to various semiconductor fabrication processes.