Abstract: A new method of forming a back diffused resistive load element is achieved. A pattern of gate electrodes and interconnection lines is formed overlying a semiconductor substrate. Source and drain regions are formed within the semiconductor substrate. An interpoly oxide layer is deposited overlying the top surfaces of the semiconductor substrate and etched away where it is not covered by a mask to provide an opening to a drain region within the semiconductor substrate and exposing a portion of a gate electrode wherein a spacer comprising interpoly oxide is left on the sidewall of the exposed gate electrode within the opening. In order to remove the interpoly oxide spacer, the interpoly oxide layer is overetched whereby the top portion of the drain region in the semiconductor substrate is etched away along with a portion of the dopant. First ions are implanted into the drain region and the exposed portion of the gate electrode.

Abstract: A new method of forming a polysilicon resistor is achieved. Polysilicon gate structures and source/drain regions are formed in and on a semiconductor substrate. A passivation layer is formed overlying the gate structures. A contact window is opened to the drain portion of the source/drain region. A resistor is formed within the contact window as follows. A nitride layer is deposited over the passivation layer and within the contact window. The nitride layer is etched back to form nitride sidewalls within the contact window. A layer of polysilicon is deposited over the passivation layer and within the contact window. The polysilicon layer is etched back to leave the polysilicon only within the contact opening completing formation of the resistor. A second contact window is opened to the source portion of the source/drain region. A barrier metal layer is deposited over the passivation layer, over the resistor, and within the second contact window.

Abstract: A process and for fabricating field oxide isolation pattern with field implants associated therewith that can be used for increasingly smaller dimensional elements, for example in feature sizes of 0.8 micrometers or less, and simpler processing than the prior art is described. A semiconductor substrate is provided. A multilayer oxidation masking structure of a thin silicon oxide layer, a silicon nitride layer, and a polycrystalline silicon layer is formed. The multilayer oxidation mask is patterned by removing the silicon nitride layer and the polycrystalline silicon layer from the areas designated to have field oxide isolation grown therein to form a narrow opening. The structure is exposed to an oxidizing environment such that the polysilicon oxide layer forms an "overhang" over part of the field isolation region. Ion implanting in a vertical direction is accomplished to form the field implant in the silicon surface of the dimension of the narrow opening less the overhang.

Abstract: A method for fabricating an integrated circuit having a double polysilicon capacitors and metal oxide silicon field effect devices which are compatible to one micrometer or less processing is described. First, a pattern of recessed oxide isolation is formed on the surface of a silicon substrate. The pattern separates surface regions of silicon from other such regions. A gate dielectric layer is formed on the surface of surface regions of the silicon with a suitable dopant concentration. A first polysilicon layer is formed over the gate dielectric layer and over the field oxide having a suitable doping concentration. An interpoly dielectric layer is formed over the surface of the first polysilicon layer. A second poly silicon layer is formed over the interpoly dielectric layer having a suitable doping concentration. The second polysilicon layer is patterned using a first resist masking and suitable etching to leave only the top plate of the capacitor in the second polysilicon layer.

Abstract: A method of providing a planar or iso-planar surface to the interlevel dielectric layer between metal layers of a multilevel MOS wafer includes applying a first dielectric over the first metal layer, applying a layer of spin-on glass over the first dielectric layer, etching the spin-on glass layer in an etch process in which the rate of etch of the spin-on glass is approximately the same as the rate of etch of the first dielectric to reveal at least a portion of the first dielectric layer. A second dielectric layer is placed over the surface of the first dielectric. Vias may then be defined through the dielectric layers, and the second metal layer may be applied over the relatively smooth surface of the second dielectric layer.

Abstract: A method of visually monitoring the change in dimensions of elements on a surface of a semiconductor body during processing is provided. A fixed pattern of scale images on the surface with a predetermined distance between images, together with a wedge-shaped element is provided on the surface. The wedge element has an apex adjacent one of the images and extends in a direction along other ones of the images. The semiconductor body is processed and the dimensions of the wedge-shaped element (as well as the scale image) change. One may then subsequently visually inspect the wedge shaped element with respect to the pattern of images to determine the extent of the change in dimension of the wedge shaped element during processing.