Patents by Inventor Keh-Yuh Yu

Keh-Yuh Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6884684
    Abstract: A high density trench power-MOSFET is described in the present invention. The power-MOSFET has a substrate, first and second epi-layers sequentially formed over the substrate and a trench type gate electrode. A silicon nitride layer is formed over the gate electrode to prevent an electrical connecting between the gate electrode and the metal layer formed in a later process.
    Type: Grant
    Filed: May 6, 2003
    Date of Patent: April 26, 2005
    Assignee: Advanced Power Electronics Corp.
    Inventors: Lin-Chung Huang, Keh-Yuh Yu
  • Publication number: 20040175889
    Abstract: A high density trench power MOSFET is described in the present invention. The power-MOSFET has a substrate, first and second epi-layers sequentially formed over the substrate and a trench type gate electrode. A silicon nitride layer is formed over the gate electrode to prevent an electrical connecting between the gate electrode and the metal layer formed in a later process.
    Type: Application
    Filed: May 6, 2003
    Publication date: September 9, 2004
    Inventors: Lin-Chung Huang, Keh-Yuh Yu
  • Patent number: 6777295
    Abstract: A method of fabricating trench power MOSFET is described. A first etching step is performed on a substrate to form a plurality of trenches and the substrate has a first doped region and a second doped region and serves as a drain region. A gate oxide layer and a polysilicon layer are then sequentially formed on the second doped region to create a gate region. Subsequent performance of a second etching step utilizes a mask layer to overlap the polysilicon layer. A portion of the second doped region is exposed and the exposed portion defines a base region. The polysilicon layer is etched to expose the gate oxide layer and the base region is simultaneously etched to remove a portion of the second doped region to expose the first doped region for forming an aligned source region. A contact region in the source region is finally formed to fabricate the trench power MOSFET.
    Type: Grant
    Filed: August 12, 2003
    Date of Patent: August 17, 2004
    Assignee: Advanced Power Electronics Corp.
    Inventors: Jau-Yan Lin, Keh-Yuh Yu