Abstract: A fast-response photovoltaic (PV) simulator based on an improved deadbeat predictive current control (DPCC). Compared to actual PV modules, there is a response time at the output of the PV simulation. Currently widely used PV simulation have a long response time, which cannot meet the performance testing requirements of high-performance grid-connected PV inverters. Based on the energy balance of the inductor during the absorption and dissipation phases, the current control law of the output inductor in the PV simulation was studied in a single switching period, thereby establishing the required DPCC model. An integral compensation eliminates the steady-state error in current tracking caused by nonlinear factors such as time delay and mismatched parameters, enabling its wide application in engineering. For the proposed PV simulator, the transient response time can be reduced to 1.1 ms and significantly shorter than widely used PV simulation.

Abstract: Genetic circuits that control transgene expression in response to pre-defined transcriptional cues would enable the development of smart therapeutics. The present disclosure relates to engineered programmable single-transcript RNA sensors in which adenosine deaminases acting on RNA (ADARs) autocatalytically convert trigger hybridization into a translational output. This system amplifies the signal from editing by endogenous ADAR through a positive feedback loop. Amplification is mediated by the expression of a hyperactive, minimal ADAR variant and its recruitment to the edit site via an orthogonal RNA targeting mechanism. This topology confers high dynamic range, low background, minimal off-target effects, and a small genetic footprint. The circuits and systems disclosed herein leverage an ability to detect single nucleotide polymorphisms and modulate translation in response to endogenous transcript levels in mammalian cells.

Abstract: A semiconductor structure includes a first sidewall spacer on sidewalls of a first device structure on a surface of a substrate and a second sidewall spacer on sidewalls of a second device structure on the surface of the substrate. The first sidewall spacer includes a first liner layer on sidewalls of the first device structure, a first oxide spacer on the first liner layer and on the surface of the substrate, and a first etch stop layer on the first oxide spacer. The second sidewall spacer includes a second liner layer on sidewalls of the second device structure, an inner oxide spacer on the second liner layer and on the surface of the substrate, a second etch stop layer on the inner oxide layer, and an outer oxide spacer on the second etch stop layer.