Patents by Inventor Kei Fukui

Kei Fukui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11017957
    Abstract: The dye-sensitized solar cell comprises a first electrode including a porous semiconductor layer supporting a dye; and a second electrode serving as a counter electrode of the first electrode. The second electrode includes a counter electrode conductive layer containing an absorbent supporting a dye that is the same as or different from the dye supported by the porous semiconductor layer.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: May 25, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Atsushi Fukui, Tomohisa Yoshie, Kei Kasahara, Naoto Nishimura, Daisuke Toyoshima
  • Patent number: 10396020
    Abstract: A board includes a plate-shaped member having a first wiring pattern, a first resin layer formed on a first surface of the plate-shaped member, the first surface having the first wiring pattern, a second resin layer stacked on the first resin layer, and a component fixed to the second resin layer in which a second wiring pattern formed on a second surface of the component is buried.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: August 27, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Kei Fukui, Youichi Hoshikawa, Hiromitsu Kobayashi, Hidehiko Fujisaki, Seigo Yamawaki, Masateru Koide, Manabu Watanabe, Daisuke Mizutani, Tomoyuki Akahoshi
  • Publication number: 20190053385
    Abstract: A circuit board includes: an insulating layer; a capacitor which is provided in the insulating layer and which includes a dielectric layer, a first conductor layer provided on a first surface of the dielectric layer and including an opening part, and a second conductor layer provided on a second surface opposite to the first surface of the dielectric layer and including a recess part at a position corresponding to the opening part; and a conductor via provided in the insulating layer, penetrating the dielectric layer, the opening part and the recess part, being in contact with the recess part, and being smaller than the opening part in plan view.
    Type: Application
    Filed: October 17, 2018
    Publication date: February 14, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Masaharu Furuyama, Daisuke Mizutani, Tomoyuki AKAHOSHI, Masateru Koide, MANABU WATANABE, Seigo Yamawaki, Kei FUKUI
  • Publication number: 20180315687
    Abstract: A board includes a plate-shaped member having a first wiring pattern, a first resin layer formed on a first surface of the plate-shaped member, the first surface having the first wiring pattern, a second resin layer stacked on the first resin layer, and a component fixed to the second resin layer in which a second wiring pattern formed on a second surface of the component is buried.
    Type: Application
    Filed: April 19, 2018
    Publication date: November 1, 2018
    Applicant: FUJITSU LIMITED
    Inventors: Kei FUKUI, Youichi Hoshikawa, Hiromitsu KOBAYASHI, Hidehiko Fujisaki, Seigo Yamawaki, Masateru Koide, MANABU WATANABE, Daisuke Mizutani, Tomoyuki AKAHOSHI
  • Patent number: 10109571
    Abstract: A wiring substrate includes a laminated sheet including a first conductor pattern, an inorganic dielectric layer, and a second conductor pattern. The first conductor pattern, the inorganic dielectric layer, and the second conductor pattern are laminated in this order. Also, the first conductor pattern is divided into a plurality of regions.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: October 23, 2018
    Assignees: FUJITSU LIMITED, SONY CORPORATION
    Inventors: Kei Fukui, Kazuya Arai, Koji Komemura, Kazuhiko Iijima, Kenichiro Abe, Shinji Rokuhara, Shuichi Oka
  • Publication number: 20170103944
    Abstract: A wiring substrate includes a laminated sheet including a first conductor pattern, an inorganic dielectric layer, and a second conductor pattern. The first conductor pattern, the inorganic dielectric layer, and the second conductor pattern are laminated in this order. Also, the first conductor pattern is divided into a plurality of regions.
    Type: Application
    Filed: September 28, 2016
    Publication date: April 13, 2017
    Applicants: FUJITSU LIMITED, SONY CORPORATION
    Inventors: Kei FUKUI, Kazuya Arai, Koji Komemura, Kazuhiko Iijima, Kenichiro Abe, Shinji Rokuhara, Shuichi Oka
  • Publication number: 20170020000
    Abstract: A component-mounted board includes: a substrate; an electronic component disposed over the substrate; and a conductive via formed in the substrate to be in contact with a bottom surface and a side surface of an electrode of the electronic component in a state where the electronic component is disposed over the substrate.
    Type: Application
    Filed: July 11, 2016
    Publication date: January 19, 2017
    Applicant: FUJITSU LIMITED
    Inventors: TAKATOYO YAMAKAMI, Naoki Ishikawa, Kimio Nakamura, Kenji Iida, Hiromitsu Kobayashi, Kei Fukui
  • Patent number: 9386700
    Abstract: A method of manufacturing a circuit board includes forming a first electrode on a support substrate, covering the support substrate and the first electrode with a first insulating layer, polishing the first insulating layer to expose a first surface of the first electrode, forming a first wiring on the first insulating layer after exposing the first surface of the first electrode, the first wiring being connected to the first electrode, and removing the support substrate to expose a second surface of the first electrode after forming the first wiring.
    Type: Grant
    Filed: January 12, 2015
    Date of Patent: July 5, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Kazuya Arai, Shinpei Ikegami, Hitoshi Suzuki, Kei Fukui
  • Patent number: 9192058
    Abstract: A method for manufacturing a component built-in substrate is disclosed, which can attain high densities of components and wirings. The method includes: mounting electronic components on a predetermined member with its surface being provided with a first layer enabled to be exfoliated; stacking a second layer to fill the electronic components further on the first layer; exfoliating and removing the predetermined member from a stacked body configured by stacking the second layer on the first layer; and forming a via to penetrate the first layer and conduct to the electronic components from a surface of the surfaces of the stacked body, from which the predetermined member is removed.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: November 17, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Kei Fukui, Koji Komemura, Hiromitsu Kobayashi, Mitsuo Denda
  • Publication number: 20150195918
    Abstract: A method for manufacturing a component built-in substrate is disclosed, which can attain high densities of components and wirings. The method includes: mounting electronic components on a predetermined member with its surface being provided with a first layer enabled to be exfoliated; stacking a second layer to fill the electronic components further on the first layer; exfoliating and removing the predetermined member from a stacked body configured by stacking the second layer on the first layer; and forming a via to penetrate the first layer and conduct to the electronic components from a surface of the surfaces of the stacked body, from which the predetermined member is removed.
    Type: Application
    Filed: December 19, 2014
    Publication date: July 9, 2015
    Inventors: Kei FUKUI, Koji Komemura, Hiromitsu KOBAYASHI, Mitsuo DENDA
  • Publication number: 20150124423
    Abstract: A method of manufacturing a circuit board includes forming a first electrode on a support substrate, covering the support substrate and the first electrode with a first insulating layer, polishing the first insulating layer to expose a first surface of the first electrode, forming a first wiring on the first insulating layer after exposing the first surface of the first electrode, the first wiring being connected to the first electrode, and removing the support substrate to expose a second surface of the first electrode after forming the first wiring.
    Type: Application
    Filed: January 12, 2015
    Publication date: May 7, 2015
    Inventors: Kazuya ARAI, Shinpei IKEGAMI, Hitoshi SUZUKI, Kei FUKUI
  • Patent number: 8959758
    Abstract: A method of manufacturing a circuit board includes forming a first electrode on a support substrate, covering the support substrate and the first electrode with a first insulating layer, polishing the first insulating layer to expose a first surface of the first electrode, forming a first wiring on the first insulating layer after exposing the first surface of the first electrode, the first wiring being connected to the first electrode, and removing the support substrate to expose a second surface of the first electrode after forming the first wiring.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: February 24, 2015
    Assignee: Fujitsu Limited
    Inventors: Kazuya Arai, Shinpei Ikegami, Hitoshi Suzuki, Kei Fukui
  • Patent number: 8800142
    Abstract: A semiconductor chip mounting layer of a package substrate unit includes an insulation layer, a conductive seed metal layer formed on the top surface of the insulation layer, conductive pads formed on the top surface of the conductive seed metal layer, metal posts formed substantially in the central portion on the top surface of the conductive pads, and a solder resist layer that is formed to surround the conductive pads and the metal posts.
    Type: Grant
    Filed: February 8, 2011
    Date of Patent: August 12, 2014
    Assignee: Fujitsu Limited
    Inventors: Hnin Nway San Nang, Kazuya Arai, Kei Fukui, Shinpei Ikegami, Yasuhito Takahashi, Hideaki Yoshimura, Hitoshi Suzuki
  • Publication number: 20120241206
    Abstract: A method of manufacturing a circuit board includes forming a first electrode on a support substrate, covering the support substrate and the first electrode with a first insulating layer, polishing the first insulating layer to expose a first surface of the first electrode, forming a first wiring on the first insulating layer after exposing the first surface of the first electrode, the first wiring being connected to the first electrode, and removing the support substrate to expose a second surface of the first electrode after forming the first wiring.
    Type: Application
    Filed: March 22, 2012
    Publication date: September 27, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Kazuya ARAI, Shinpei IKEGAMI, Hitoshi SUZUKI, Kei FUKUI
  • Publication number: 20120067635
    Abstract: A semiconductor chip mounting layer of a package substrate unit includes an insulation layer, a conductive seed metal layer formed on the top surface of the insulation layer, conductive pads formed on the top surface of the conductive seed metal layer, metal posts formed substantially in the central portion on the top surface of the conductive pads, and a solder resist layer that is formed to surround the conductive pads and the metal posts.
    Type: Application
    Filed: February 8, 2011
    Publication date: March 22, 2012
    Applicant: Fujitsu Limited
    Inventors: Hnin Nway San Nang, Kazuya Arai, Kei Fukui, Shinpei Ikegami, Yasuhito Takahashi, Hideaki Yoshimura, Hitoshi Suzuki