Abstract: A detector includes a first electrode, second electrodes forming a flow path for charged particles between the first electrode and the second electrodes, third electrodes configured to collect the charged particles, and a fourth electrode having a sheet resistance higher than sheet resistances of the second electrodes. The fourth electrode has one end portion having a first potential in a third direction and another end portion having a second potential lower than the first potential in the third direction, the fifth electrode included in the second electrodes is connected to the fourth electrode, the sixth electrode included in the second electrodes is connected to the fourth electrode, a seventh electrode included in the third electrodes is arranged side by side with the fifth electrode along a first direction, and an eighth electrode included in the third electrodes is arranged side by side with the sixth electrode along the first direction.

Abstract: A detector includes a first electrode, a second electrode facing the first electrode with a space and forming a flow path for charged particles as objects to be detected between the first electrode and the second electrode, a third electrode arranged side by side with the second electrode on a downstream side in the flow path with respect to the second electrode and configured to collect the charged particles, and a potential supply circuit configured to supply a potential to at least one of the first electrode and the second electrode, in which the potential supply circuit includes a first inductor including a first input portion and a first output portion, and a second inductor including a second input portion and a second output portion, the first input portion of the first inductor is connected to a DC power supply, and the second input portion of the second inductor is connected to the first electrode or the second electrode.

Abstract: A detection cell includes a pair of filter electrodes, disposed separated from and opposing each other. One of the pair of filter electrodes includes a first region provided following a flow direction of an object of measurement introduced between the filter electrodes, and a second region that is provided arrayed with the first region regrading an intersecting direction intersecting the flow direction, and that protrudes to a position at which a distance of separation as to another of the pair of filter electrodes is smaller than that of the first region. First and second downstream-side electrodes are respectively disposed on downstream sides of the first and second regions, in the flow direction, and are separated from each other regarding the intersecting direction. First and second opposing electrodes are disposed on the downstream side from the other of the pair of filter electrodes, and oppose the first and second downstream-side electrodes.

Abstract: An electrowetting device has an active matrix substrate including a plurality of first electrodes arrayed in a matrix shape, a plurality of TFTs, a plurality of first wiring lines extending along a row direction, and a plurality of second wiring lines extending along a column direction. The plurality of TFTs are disposed so as to have at least one of first and second relative arrangements. The first relative arrangement is a relative arrangement where two or more TFTs that are connected to any one of the plurality of first wiring lines alternately include, along the row direction: TFTs that are connected to the first electrodes belonging to one of a pair of rows adjoining the one first wiring line; and TFTs that are connected to the first electrodes belonging to the other row.

Abstract: An analyzer includes: a flow path component providing a flow path through which a sample is supplied from an inlet end thereof toward an outlet end thereof; an ionization unit that ionizes the sample flowing in the flow path to produce ions; a pair of voltage application electrodes located opposite each other across the flow path and closer to the outlet end than the ionization unit is located close to the outlet end, an asymmetric-waveform, high-frequency voltage being applied to the ions through the pair of voltage application electrodes; a detection electrode located closer to the outlet end than the pair of voltage application electrodes is located close to the outlet end; a deflection electrode located opposite the detection electrode across the flow path, the deflection electrode generating a DC electric field that moves the ions toward the detection electrode; and a reference electrode located not opposite the deflection electrode.

Abstract: An electrowetting device of the present disclosure includes: an electrode substrate including a first substrate, a plurality of first electrodes formed above the first substrate, a dielectric layer formed on the first electrodes, and a first hydrophobic layer formed on the dielectric layer; a counter substrate disposed across a predetermined clearance from the electrode substrate, and including a second substrate, a second electrode formed on the second substrate, and a second hydrophobic layer formed on the second electrode; and a seal attaching the electrode substrate and the counter substrate together, and defining the predetermined clearance between the first hydrophobic layer and the second hydrophobic layer.

Abstract: An electrowetting device has an active matrix substrate including a plurality of first electrodes arrayed in a matrix shape, a plurality of TFTs, a plurality of first wiring lines extending along a row direction, and a plurality of second wiring lines extending along a column direction. The plurality of TFTs are disposed so as to have at least one of first and second relative arrangements. The first relative arrangement is a relative arrangement where two or more TFTs that are connected to any one of the plurality of first wiring lines alternately include, along the row direction: TFTs that are connected to the first electrodes belonging to one of a pair of rows adjoining the one first wiring line; and TFTs that are connected to the first electrodes belonging to the other row.

Abstract: A tip edge (31) of an FPC (30E) bonded at a most outward position in an arrangement direction (30D) of a plurality of FPCs (30) has an edge (32) inclined relative to an edge (3e) of a terminal region (3T) to face a center of a display panel (X). An IC chip (20E) facing the tip edge (31) of the FPC (30E) bonded at the most outward position is arranged parallel to the inclined edge (32) of the FPC (30E).

Abstract: A tip edge (31) of an FPC (30E) bonded at a most outward position in an arrangement direction (30D) of a plurality of FPCs (30) has an edge (32) inclined relative to an edge (3e) of a terminal region (3T) to face a center of a display panel (X). An IC chip (20E) facing the tip edge (31) of the FPC (30E) bonded at the most outward position is arranged parallel to the inclined edge (32) of the FPC (30E).

Abstract: An object is shortening a clock fall-rise period while suppressing an increase in a circuit area, an increase in current consumption, and a cost increase, without generating an abnormal operation, in a shift register within a monolithic gate driver. In a shift register (410) that operates based on four-phase clock signals, including two-phase clock signals (GCK1, GCK3) that are provided to odd-order stages and two-phase clock signals (GCK2, GCK4) that are provided to even-order stages, of which phases are shifted by 90 degrees from each other, a potential of a first clock (CKA) appears as a potential of a scanning signal (GOUT), when a potential of a first node is at a high level, in each stage. In this configuration, the potential of the first node included in each stage is set to a high level based on a pulse of a scanning signal outputted from a pre-stage, and is set to a low level based on a pulse of a scanning signal outputted from a third stage after a stage concerned.

Abstract: Each stage that constitutes a shift register includes an output-control thin-film transistor for increasing a potential of a scanning signal based on a first clock (CKA), two thin-film transistors for increasing a potential of a first node connected to a gate terminal of the output-control thin-film transistor, based on a scanning signal outputted from a pre-stage/a latter stage, and two thin-film transistors for decreasing a potential of the first node, based on a scanning signal outputted from a third stage after/a third stage before a stage concerned. The shift register operates based on four-phase clock signals, including two-phase clock signals that are provided to odd-order stages and two-phase clock signals that are provided to even-order stages, of which phases are shifted by 90 degrees from each other.

Abstract: The present invention provides a display panel having decreased cost and current consumption by decreasing the number of data signal lines from the conventional number, a display device including the display panel, and a method of driving the display device. Each pixel formation portion (10) included in a display unit (200) of a display device is configured to arrange three sub-pixel formation portions (1r, 1g, 1b) for forming sub-pixels of mutually different color components in a data signal line extension direction. Each one data signal line (30) is arranged between a sub-pixel formation portion vertical string (3) in an odd-order from a front of a scanning signal line extension direction and a sub-pixel formation portion vertical string (3) adjacent to the sub-pixel formation portion vertical string (3) at the back of the scanning signal line extension direction. Sub-pixel formation portion vertical strings (3, 3) positioned at both sides of each data signal line (30) are connected to the data signal line.

Abstract: An object is to provide at low cost a Power-supply circuit that can generate positive and negative analog power source voltages of which absolute values of voltage values are equal. A Power-supply circuit (210) is configured by a DCDC converter circuit (212) and a charge pump circuit (214). The charge pump circuit (214) includes a diode (D3) that passes a current when a control switch (51) is in an off state, and a diode (D4) that passes a current when the control switch (51) is in an on state. A DCDC converter circuit (212) includes two diodes (D1, D2) that pass a current when the control switch (S1) is in an off state. A rectifying unit that includes the diodes (D1, D2) is configured such that a forward drop voltage of the rectifying unit becomes equal to a sum of a forward drop voltage of the diode (D3) and a forward drop voltage of the diode (D4).

Abstract: In a shift register that operates based on four-phase clock signals, including two-phase clock signals that are provided to odd-order stages and two-phase clock signals that are provided to even-order stages, of which phases are shifted by 90 degrees from each other, a potential of a first clock appears as a potential of a scanning signal, when a potential of a first node is at a high level, in each stage. In this configuration, the potential of the first node included in each stage is set to a high level based on a pulse of a scanning signal outputted from a pre-stage, and is set to a low level based on a pulse of a scanning signal outputted from a third stage after a stage concerned.

Abstract: Each stage that constitutes a shift register includes an output-control thin-film transistor for increasing a potential of a scanning signal based on a first clock (CKA), two thin-film transistors for increasing a potential of a first node connected to a gate terminal of the output-control thin-film transistor, based on a scanning signal outputted from a pre-stage/a latter stage, and two thin-film transistors for decreasing a potential of the first node, based on a scanning signal outputted from a third stage after/a third stage before a stage concerned. The shift register operates based on four-phase clock signals, including two-phase clock signals that are provided to odd-order stages and two-phase clock signals that are provided to even-order stages, of which phases are shifted by 90 degrees from each other.

Abstract: Provided is a liquid crystal display device performing a precharge and having a function of switching an order for selecting scanning lines, in which such as flicker and burn-in can be prevented from being produced. A scanning line drive circuit selects scanning lines either in ascending order or in descending order based on an order of arrangement according to a shift direction signal, and causes selection periods of the scanning lines to be partially overlapped for a precharge. A data line drive circuit applies voltages of different polarities to data lines by frame and by data line. A common voltage generating circuit generates two types of voltages whose levels are independently adjustable, selects one of the two voltages according to a scan selection signal and applies the selected voltage to a common electrode of a liquid crystal panel. As the common voltage generating circuit, a D/A converter may be used.

Abstract: In at least one embodiment, under a non-load condition of a first supply line for a first clock signal and a second supply line for a second clock signal, a fall time of a clock pulse of the first clock signal, which is supplied to the first supply line, is longer than that of the second clock signal, which is supplied to the second supply line.

Abstract: A control section prepares a control signal and supplies the control signal to a control terminal of a first switching element, the control signal causing the first switching element to turn on in accordance with a non-active voltage level of a storage node and an active voltage level of a second clock signal which active voltage level is obtained in a period in which the second clock signal is active.