Abstract: An electrostatic discharge protection circuit for an integrated circuit and a method for electrostatic discharge protection thereof are disclosed. The integrated circuit includes a power source, a ground, a signal input, and a signal output. The integrated circuit further comprises one or more essentially identically configured electrostatic discharge protection circuits, configured to provide electrostatic discharge protection between any two of the power source, the ground, the signal input, and the signal output. A method of providing electrostatic discharge protection includes providing one or more essentially identically configured electrostatic discharge protection circuits coupled between and providing electrostatic discharge protection for any two of the power source, the ground, the signal input, and the signal output. The disclosed integrated circuit and method provide advantages of simplifying the integrated circuit design and reducing design time.

Abstract: An integral multifunction chip is provided. The integral multifunction chip includes an electronic fuse and an interface fuse. The interface fuse and the electronic fuse are disposed in parallel and integrated in a single chip. In a case where only a single chip is provided, the integral multifunction chip of the present disclosure can be selectively operated in a working mode of the electronic fuse or the interface fuse, so that convenience of use of the integral multifunction chip can be improved.

Abstract: A method and a system for developing semiconductor device fabrication processes are provided. The developments of vertical and lateral semiconductor device fabrication processes can be integrated in the system. First, according to a target semiconductor device and a specification thereof, an initial target model and a general database are captured. The initial target model and the general database are compared to obtain a corresponding relationship. According to the corresponding relationship, multiple fixed fabrication parameters of the general database are applied to the initial target model, such that at least one adjustable parameter is defined. Thereafter, the parameter is set according to a setting instruction received through a user interface to produce a target model to be simulated. A simulation test is performed with the target model, and the adjustable parameter is modified until the simulation result of the target model satisfies a standard result.

Abstract: A method and a system for developing semiconductor device fabrication processes are provided. The developments of vertical and lateral semiconductor device fabrication processes can be integrated in the system. First, according to a target semiconductor device and a specification thereof, an initial target model and a general database are captured. The initial target model and the general database are compared to obtain a corresponding relationship. According to the corresponding relationship, multiple fixed fabrication parameters of the general database are applied to the initial target model, such that at least one adjustable parameter is defined. Thereafter, the parameter is set according to a setting instruction received through a user interface to produce a target model to be simulated. A simulation test is performed with the target model, and the adjustable parameter is modified until the simulation result of the target model satisfies a standard result.

Abstract: An integral multifunction chip is provided. The integral multifunction chip includes an electronic fuse and an interface fuse. The interface fuse and the electronic fuse are disposed in parallel and integrated in a single chip. In a case where only a single chip is provided, the integral multifunction chip of the present disclosure can be selectively operated in a working mode of the electronic fuse or the interface fuse, so that convenience of use of the integral multifunction chip can be improved.

Abstract: A method and a system for developing semiconductor device fabrication processes are provided. The developments of vertical and lateral semiconductor device fabrication processes can be integrated in the system. First, according to a target semiconductor device and a specification thereof, an initial target model and a general database are captured. The initial target model and the general database are compared to obtain a corresponding relationship. According to the corresponding relationship, multiple fixed fabrication parameters of the general database are applied to the initial target model, such that at least one adjustable parameter is defined. Thereafter, the parameter is set according to a setting instruction received through a user interface to produce a target model to be simulated. A simulation test is performed with the target model, and the adjustable parameter is modified until the simulation result of the target model satisfies a standard result.

Abstract: An integral multifunction chip is provided. The integral multifunction chip includes an electronic fuse and an interface fuse. The interface fuse and the electronic fuse are disposed in parallel and integrated in a single chip. In a case where only a single chip is provided, the integral multifunction chip of the present disclosure can be selectively operated in a working mode of the electronic fuse or the interface fuse, so that convenience of use of the integral multifunction chip can be improved.

Abstract: A DRAM cell includes a transistor, a first diode and a second diode. The transistor has a gate electrically coupled to a word line of an address decoder and a drain electrically coupled to a bit line of the address decoder. The bit line is coupled to a power supply voltage. An anode and a cathode of the first diode are coupled to a cathode and an anode of the second diode, respectively. Each of the first diode and the second diode is coupled at a first end to a source of the transistor at a first node, and at a second end to a node voltage at the second node. A DRAM device includes an address decoder and DRAM cells. A storage method for a DRAM device includes writing data into the DRAM cells and reading data from the DRAM cells.

Abstract: An electrostatic discharge protection circuit for an integrated circuit and a method for electrostatic discharge protection thereof are disclosed. The integrated circuit includes a power source, a ground, a signal input, and a signal output. The integrated circuit further comprises one or more essentially identically configured electrostatic discharge protection circuits, configured to provide electrostatic discharge protection between any two of the power source, the ground, the signal input, and the signal output. A method of providing electrostatic discharge protection includes providing one or more essentially identically configured electrostatic discharge protection circuits coupled between and providing electrostatic discharge protection for any two of the power source, the ground, the signal input, and the signal output. The disclosed integrated circuit and method provide advantages of simplifying the integrated circuit design and reducing design time.

Abstract: A DRAM cell includes a transistor, a first diode and a second diode. The transistor has a gate electrically coupled to a word line of an address decoder and a drain electrically coupled to a bit line of the address decoder. The bit line is coupled to a power supply voltage. An anode and a cathode of the first diode are coupled to a cathode and an anode of the second diode, respectively. Each of the first diode and the second diode is coupled at a first end to a source of the transistor at a first node, and at a second end to a node voltage at the second node. A DRAM device includes an address decoder and DRAM cells. A storage method for a DRAM device includes writing data into the DRAM cells and reading data from the DRAM cells.

Abstract: A method and a system for developing semiconductor device fabrication processes are provided. The developments of vertical and lateral semiconductor device fabrication processes can be integrated in the system. First, according to a target semiconductor device and a specification thereof, an initial target model and a general database are captured. The initial target model and the general database are compared to obtain a corresponding relationship. According to the corresponding relationship, multiple fixed fabrication parameters of the general database are applied to the initial target model, such that at least one adjustable parameter is defined. Thereafter, the parameter is set according to a setting instruction received through a user interface to produce a target model to be simulated. A simulation test is performed with the target model, and the adjustable parameter is modified until the simulation result of the target model satisfies a standard result.

Abstract: An integral multifunction chip is provided. The integral multifunction chip includes an electronic fuse and an interface fuse. The interface fuse and the electronic fuse are disposed in parallel and integrated in a single chip. In a case where only a single chip is provided, the integral multifunction chip of the present disclosure can be selectively operated in a working mode of the electronic fuse or the interface fuse, so that convenience of use of the integral multifunction chip can be improved.

Abstract: A semiconductor device includes a semiconductor substrate and a first semiconductor element. The semiconductor substrate has a circuit core area. The first semiconductor element is arranged on the semiconductor substrate and at least partially surrounds the periphery of the circuit core area. A layout area of the first semiconductor element is larger than a layout area of any of the semiconductor elements in the circuit core area.

Abstract: Provided is a transient voltage suppressor including a substrate, a well region of a first conductivity type, a first doped region of a second conductivity type, and a second doped region of the second conductivity type. The substrate is electrically floating. The well region is located in the substrate. The first doped region is located in the well region to form a diode, and the first doped region is electrically connected to a first voltage. The second doped region is located in the well region, and the second doped region is electrically connected to a second voltage.

Abstract: A transmitter, a common mode transceiver using the same, and an operating method thereof are provided. The transmitter includes a first transistor group and a second transistor group. The first transistor group includes a first transistor connected in series with a second transistor, wherein the second transistor is applied a first well-tracking control. The second transistor group includes a third transistor connected in series with a fourth transistor, wherein the third transistor is applied a second well-tracking control. There is an output node between the first transistor group and the second transistor group, and the second transistor and the third transistor are coupled to the output node. The present invention can effectively block leakage paths in common mode operation, and can enhance ESD protection capability.

Abstract: A transmitter, a common mode transceiver using the same, and an operating method thereof are provided. The transmitter includes a first transistor group and a second transistor group. The first transistor group includes a first transistor connected in series with a second transistor, wherein the second transistor is applied a first well-tracking control. The second transistor group includes a third transistor connected in series with a fourth transistor, wherein the third transistor is applied a second well-tracking control. There is an output node between the first transistor group and the second transistor group, and the second transistor and the third transistor are coupled to the output node. The present invention can effectively block leakage paths in common mode operation, and can enhance ESD protection capability.

Abstract: A semiconductor device includes a semiconductor substrate and a first semiconductor element. The semiconductor substrate has a circuit core area. The first semiconductor element is arranged on the semiconductor substrate and at least partially surrounds the periphery of the circuit core area. A layout area of the first semiconductor element is larger than a layout area of any of the semiconductor elements in the circuit core area.

Abstract: Provided is a transient voltage suppressor including a substrate, a well region of a first conductivity type, a first doped region of a second conductivity type, and a second doped region of the second conductivity type. The substrate is electrically floating. The well region is located in the substrate. The first doped region is located in the well region to form a diode, and the first doped region is electrically connected to a first voltage. The second doped region is located in the well region, and the second doped region is electrically connected to a second voltage.

Abstract: A dual triggered silicon controlled rectifier (DTSCR) comprises: a semiconductor substrate; a well region, a first N+ diffusion region, a first P+ diffusion region, a second N+ diffusion region, a second P+ diffusion region, a third P+ diffusion region, positioned in one side of the DTSCR and across the well region and semiconductor substrate; a third N+ diffusion region, positioned in another side of the DTSCR and across the well region and the semiconductor substrate; a first gate, positioned above the semiconductor substrate between the first P+ diffusion region and the third P+ diffusion region, utilized as a P-type trigger node to receive a first trigger current or a first trigger voltage; and a second gate, positioned above the well region between the second N+ diffusion region and the third N+ diffusion region, utilized as an N-type trigger node to receive a second trigger current or a second trigger voltage.

Abstract: A dual triggered silicon controlled rectifier (DTSCR) comprises: a semiconductor substrate; an N-well, a P-well, a first N+ diffusion region and a first P+ diffusion region, a second N+ diffusion region and a second P+ diffusion region, a third P+ diffusion region, positioned in one side of the DTSCR and across the N-well and the P-well; a third N+ diffusion region, positioned in another side of the DTSCR and across the N-well and the P-well; a first gate, positioned above the N-well between the second P+ diffusion region and the third P+ diffusion region, for use as a P-type trigger node to receive a first trigger current or a first trigger voltage; and a second gate, positioned above the P-well between the first N+ diffusion region and the third N+ diffusion region, for use as an N-type trigger node to receive a second trigger current or a second trigger voltage.