Abstract: A cutting apparatus includes a cutting dust collection box that collects cutting dust and a cutting dust guide plate that is disposed on the downstream side in a processing feed direction relative to a chuck table and receives cutting water and the cutting dust that flow to the downstream side after cutting to guide the cutting water and the cutting dust to the cutting dust collection box. A cutting dust breaking unit that breaks the cutting dust into small pieces is disposed at a position onto which the cutting dust that flows from a plate-shaped cover drops over the cutting dust guide plate.

Abstract: A cutting apparatus includes a cutting dust collection box that collects cutting dust and a cutting dust guide plate that is disposed on the downstream side in a processing feed direction relative to a chuck table and receives cutting water and the cutting dust that flow to the downstream side after cutting to guide the cutting water and the cutting dust to the cutting dust collection box. A cutting dust breaking unit that breaks the cutting dust into small pieces is disposed at a position onto which the cutting dust that flows from a plate-shaped cover drops over the cutting dust guide plate.

Abstract: A cutting apparatus includes a width measuring unit for measuring the width of a grooving groove formed in a wafer by laser grooving and the width of a cut groove formed by a cutting blade. The width measuring unit includes an imaging camera for imaging the grooving groove and the cut groove, and an illuminating unit for illuminating an area to be imaged by the imaging camera with light supplied in a predetermined light quantity. Therefore, when first light is radiated from the illuminating unit, a first image in which the grooving groove is sharply imaged can be imaged by the imaging camera, whereas when second light is radiated from the illuminating unit, a second image in which the cut groove is clearly imaged can be imaged by the imaging camera. Consequently, the grooving groove and the cut groove can be easily distinguished from each other.

Abstract: A cutting apparatus includes a width measuring unit for measuring the width of a grooving groove formed in a wafer by laser grooving and the width of a cut groove formed by a cutting blade. The width measuring unit includes an imaging camera for imaging the grooving groove and the cut groove, and an illuminating unit for illuminating an area to be imaged by the imaging camera with light supplied in a predetermined light quantity. Therefore, when first light is radiated from the illuminating unit, a first image in which the grooving groove is sharply imaged can be imaged by the imaging camera, whereas when second light is radiated from the illuminating unit, a second image in which the cut groove is clearly imaged can be imaged by the imaging camera. Consequently, the grooving groove and the cut groove can be easily distinguished from each other.

Abstract: A semiconductor integrated circuit has a nonvolatile memory and a logic circuit which uses information stored in the nonvolatile memory to perform logical operation. The nonvolatile memory comprises bit lines, word lines, and memory cells. The memory cell comprises MOS transistors whose gate electrodes are connected with a word line. Information storage is carried out according to whether one source/drain electrode of the MOS transistors is connected with a source line or floated. During other periods than a predetermined period in the operation of accessing the memory cell, the potential difference between the source/drain electrodes of the MOS transistors constituting the memory cell is zeroed. Subthreshold leakage current is prevented from passing through the memory cell on standby. During the predetermined period in accessing operation, a potential difference is produced between the source/drain electrodes of the MOS transistors.

Abstract: A semiconductor integrated circuit has a nonvolatile memory and a logic circuit which uses information stored in the nonvolatile memory to perform logical operation. The nonvolatile memory comprises bit lines, word lines, and memory cells. The memory cell comprises MOS transistors whose gate electrodes are connected with a word line. Information storage is carried out according to whether one source/drain electrode of the MOS transistors is connected with a source line or floated. During other periods than a predetermined period in the operation of accessing the memory cell, the potential difference between the source/drain electrodes of the MOS transistors constituting the memory cell is zeroed. Subthreshold leakage current is prevented from passing through the memory cell on standby. During the predetermined period in accessing operation, a potential difference is produced between the source/drain electrodes of the MOS transistors.

Abstract: A semiconductor integrated circuit has nonvolatile memory and a logic circuit which uses information stored in the nonvolatile memory to perform logical operation. The nonvolatile memory comprises bit lines, word lines, and memory cells. The memory cell comprises MOS transistors whose gate electrodes are connected with a word line. Information storage is carried out according to whether one source/drain electrode of the MOS transistors is connected with a source line or floated. During other periods than a predetermined period in the operation of accessing the memory cell, the potential difference between the source/drain electrodes of the MOS transistors constituting the memory cell is zeroed. Subthreshold leakage current is prevented from passing through the memory cell on standby. During the predetermined period in accessing operation, a potential difference is produced between the source/drain electrodes of the MOS transistors. Therefore, the bit line potential can be varied by word line selection.

Abstract: A semiconductor integrated circuit has a nonvolatile memory and a logic circuit which uses information stored in the nonvolatile memory to perform logical operation. The nonvolatile memory comprises bit lines, word lines, and memory cells. The memory cell comprises MOS transistors whose gate electrodes are connected with a word line. Information storage is carried out according to whether one source/drain electrode of the MOS transistors is connected with a source line or floated. During other periods than a predetermined period in the operation of accessing the memory cell, the potential difference between the source/drain electrodes of the MOS transistors constituting the memory cell is zeroed. Subthreshold leakage current is prevented from passing through the memory cell on standby. During the predetermined period in accessing operation, a potential difference is produced between the source/drain electrodes of the MOS transistors. Therefore, the bit line potential can be varied by word line selection.