Abstract: A semiconductor device has first wiring layers 30 and a plurality of dummy wiring layers 32 that are provided on the same level as the first wiring layers 30. The semiconductor device defines a row direction, and first virtual linear lines L1 extending in a direction traversing the row direction. The row direction and the first virtual linear lines L1 define an angle of 2-40 degrees, and the dummy wiring layers 32 are disposed in a manner to be located on the first virtual linear lines L1. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines L2 extending in a direction traversing the column direction. The column direction and the second virtual linear lines L2 define an angle of 2-40 degrees, and the dummy wiring layers 32 are disposed in a manner to be located on the second virtual linear lines L2.

Abstract: A semiconductor device has first wiring layers 30 and a plurality of dummy wiring layers 32 that are provided on the same level as the first wiring layers 30. The semiconductor device defines a row direction, and first virtual linear lines L1 extending in a direction traversing the row direction. The row direction and the first virtual linear lines L1 define an angle of 2-40 degrees, and the dummy wiring layers 32 are disposed in a manner to be located on the first virtual linear lines L1. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines L2 extending in a direction traversing the column direction. The column direction and the second virtual linear lines L2 define an angle of 2-40 degrees, and the dummy wiring layers 32 are disposed in a manner to be located on the second virtual linear lines L2.

Abstract: A semiconductor device has first wiring layers 30 and a plurality of dummy wiring layers 32 that are provided on the same level as the first wiring layers 30. The semiconductor device defines a row direction, and first virtual linear lines L1 extending in a direction traversing the row direction. The row direction and the first virtual linear lines L1 define an angle of 2-40 degrees, and the dummy wiring layers 32 are disposed in a manner to be located on the first virtual linear lines L1. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines L2 extending in a direction traversing the column direction. The column direction and the second virtual linear lines L2 define an angle of 2-40 degrees, and the dummy wiring layers 32 are disposed in a manner to be located on the second virtual linear lines L2.

Abstract: A semiconductor device has first wiring layers 30 and a plurality of dummy wiring layers 32 that are provided on the same level as the first wiring layers 30. The semiconductor device defines a row direction, and first virtual linear lines L1 extending in a direction traversing the row direction. The row direction and the first virtual linear lines L1 define an angle of 2-40 degrees, and the dummy wiring layers 32 are disposed in a manner to be located on the first virtual linear lines L1. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines L2 extending in a direction traversing the column direction. The column direction and the second virtual linear lines L2 define an angle of 2-40 degrees, and the dummy wiring layers 32 are disposed in a manner to be located on the second virtual linear lines L2.

Abstract: A semiconductor device has first wiring layers 30 and a plurality of dummy wiring layers 32 that are provided on the same level as the first wiring layers 30. The semiconductor device defines a row direction, and first virtual linear lines L1 extending in a direction traversing the row direction. The row direction and the first virtual linear lines L1 define an angle of 2-40 degrees, and the dummy wiring layers 32 are disposed in a manner to be located on the first virtual linear lines L1. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines L2 extending in a direction traversing the column direction. The column direction and the second virtual linear lines L2 define an angle of 2-40 degrees, and the dummy wiring layers 32 are disposed in a manner to be located on the second virtual linear lines L2.

Abstract: A semiconductor device has first wiring layers 30 and a plurality of dummy wiring layers 32 that are provided on the same level as the first wiring layers 30. The semiconductor device defines a row direction, and first virtual linear lines L1 extending in a direction traversing the row direction. The row direction and the first virtual linear lines L1 define an angle of 2-40 degrees, and the dummy wiring layers 32 are disposed in a manner to be located on the first virtual linear lines L1. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines L2 extending in a direction traversing the column direction. The column direction and the second virtual linear lines L2 define an angle of 2-40 degrees, and the dummy wiring layers 32 are disposed in a manner to be located on the second virtual linear lines L2.

Abstract: A semiconductor device has first wiring layers 30 and a plurality of dummy wiring layers 32 that are provided on the same level as the first wiring layers 30. The semiconductor device defines a row direction, and first virtual linear lines L1 extending in a direction traversing the row direction. The row direction and the first virtual linear lines L1 define an angle of 2-40 degrees, and the dummy wiring layers 32 are disposed in a manner to be located on the first virtual linear lines L1. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines L2 extending in a direction traversing the column direction. The column direction and the second virtual linear lines L2 define an angle of 2-40 degrees, and the dummy wiring layers 32 are disposed in a manner to be located on the second virtual linear lines L2.

Abstract: A semiconductor device has first wiring layers 30 and a plurality of dummy wiring layers 32 that are provided on the same level as the first wiring layers 30. The semiconductor device defines a row direction, and first virtual linear lines L1 extending in a direction traversing the row direction. The row direction and the first virtual linear lines L1 define an angle of 2-40 degrees, and the dummy wiring layers 32 are disposed in a manner to be located on the first virtual linear lines L1. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines L2 extending in a direction traversing the column direction. The column direction and the second virtual linear lines L2 define an angle of 2-40 degrees, and the dummy wiring layers 32 are disposed in a manner to be located on the second virtual linear lines L2.

Abstract: A semiconductor device has first wiring layers 30 and a plurality of dummy wiring layers 32 that are provided on the same level as the first wiring layers 30. The semiconductor device defines a row direction, and first virtual linear lines L1 extending in a direction traversing the row direction. The row direction and the first virtual linear lines L1 define an angle of 2-40 degrees, and the dummy wiring layers 32 are disposed in a manner to be located on the first virtual linear lines L1. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines L2 extending in a direction traversing the column direction. The column direction and the second virtual linear lines L2 define an angle of 2-40 degrees, and the dummy wiring layers 32 are disposed in a manner to be located on the second virtual linear lines L2.

Abstract: A semiconductor device includes a silicon substrate 10 having a trench isolation region 24. A plurality of dummy convex regions 32 are formed in the trench isolation region 24. The trench isolation region 24 defines a row direction and a column direction. Also, the trench isolation region 24 define first virtual linear lines L1 that extend in a direction traversing the row direction and second virtual linear lines L2 that extend in a direction traversing the column direction. The first virtual linear lines L1 and the row direction define an angle of 2-40 degree, and the second virtual linear lines L2 and the column direction define an angle of 2-40 degree. The dummy convex regions 32 are disposed on the first virtual linear lines L1 and the second virtual linear lines L2.

Abstract: A method is provided for generating mask data that is used for forming dummy convex regions in a specified pattern in a trench isolation region in a semiconductor device. Mask and computer readable recording medium are also provided. The method includes the steps of (a) setting a restriction region pattern 262 that defines a restriction region 40 in a semiconductor substrate, (b) setting dummy patterns 310 that define dummy convex regions 32, and (c) mixing the restriction region pattern 262 and the dummy patterns 310, wherein the dummy patterns 310 that at least partially overlap the restriction region pattern 262 are entirely excluded.

Abstract: A semiconductor memory device comprising first and second gate-gate connecting layers, first and second drain-drain connecting layers, and first and second drain-gate connecting layers. The first and second gate-gate connecting layers respectively connect a gate of a driver transistor to a gate of a load transistor. The first and second drain-drain connecting layers are formed over a first interlayer dielectric and have a refractory metal nitride layer. The first and second drain-drain connecting layers respectively connect a drain of the driver transistor to a drain of the load transistor. The first and second drain-gate connecting layers are formed over a second interlayer dielectric, and respectively connect the first drain-drain connecting layer to the second gate-gate connecting layer, and the second drain-drain connecting layer to the first gate-gate connecting layer.

Abstract: A semiconductor device comprising a peripheral circuit portion and a memory cell portion including a plurality of memory cells. Each memory cell has first and second gate-gate connecting layers, first and second drain-drain connecting layers, and first and second drain-gate connecting layers. The first and second gate-gate connecting layers respectively connect the gates of driver transistors to the gates of load transistors. The first and second drain-drain connecting layers are formed over a first interlayer dielectric and respectively connect the drains of driver transistors to the drains of load transistors. The first and second drain-gate connecting layers are formed over a second interlayer dielectric and respectively connect the first drain-drain connecting layer to the second gate-gate connecting layer and the second drain-drain connecting layer to the first gate-gate connecting layer.

Abstract: A semiconductor device has first wiring layers 30 and a plurality of dummy wiring layers 32 that are provided on the same level as the first wiring layers 30. The semiconductor device defines a row direction, and first virtual linear lines L1 extending in a direction traversing the row direction. The row direction and the first virtual linear lines L1 define an angle of 2-40 degrees, and the dummy wiring layers 32 are disposed in a manner to be located on the first virtual linear lines L1. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines L2 extending in a direction traversing the column direction. The column direction and the second virtual linear lines L2 define an angle of 2-40 degrees, and the dummy wiring layers 32 are disposed in a manner to be located on the second virtual linear lines L2.

Abstract: A method is provided for generating mask data that is used for forming dummy convex regions in a specified pattern in a trench isolation region in a semiconductor device. Mask and computer readable recording medium are also provided. The method includes the steps of (a) setting a restriction region pattern 262 that defines a restriction region 40 in a semiconductor substrate, (b) setting dummy patterns 310 that define dummy convex regions 32, and (c) mixing the restriction region pattern 262 and the dummy patterns 310, wherein the dummy patterns 310 that at least partially overlap the restriction region pattern 262 are entirely excluded.

Abstract: A semiconductor memory device comprising first and second gate-gate connecting layers, first and second drain-drain connecting layers, and first and second drain-gate connecting layers. The first and second gate-gate connecting layers respectively connect a gate of a driver transistor to a gate of a load transistor. The first and second drain-drain connecting layers are formed over a first interlayer dielectric and have a refractory metal nitride layer. The first and second drain-drain connecting layers respectively connect a drain of the driver transistor to a drain of the load transistor. The first and second drain-gate connecting layers are formed over a second interlayer dielectric, and respectively connect the first drain-drain connecting layer to the second gate-gate connecting layer, and the second drain-drain connecting layer to the first gate-gate connecting layer.

Abstract: A semiconductor device includes a silicon substrate 10 having a trench isolation region 24. A plurality of dummy convex regions 32 are formed in the trench isolation region 24. The trench isolation region 24 defines a row direction and a column direction. Also, the trench isolation region 24 define first virtual linear lines L1 that extend in a direction traversing the row direction and second virtual linear lines L2 that extend in a direction traversing the column direction. The first virtual linear lines L1 and the row direction define an angle of 2-40 degree, and the second virtual linear lines L2 and the column direction define an angle of 2-40 degree. The dummy convex regions 32 are disposed on the first virtual linear lines L1 and the second virtual linear lines L2.