Abstract: A memory control device 100 of the present invention includes a data storage processing unit 101 that stores, in an additional data area that is an area for storing additional data in memory-stored data including compressed data and the additional data to be stored in a memory, an error correcting code of the compressed data and compression information representing the degree of compression of the compressed data, and a read processing unit 102 that controls readout of the memory-stored data on the basis of the degree of compression represented by the compression information in the additional data area of the memory-stored data, when reading out the memory-stored data from the memory.

Abstract: A memory control device 100 of the present invention includes a data storage processing unit 101 that stores, in an additional data area that is an area for storing additional data in memory-stored data including compressed data and the additional data to be stored in a memory, an error correcting code of the compressed data and compression information representing the degree of compression of the compressed data, and a read processing unit 102 that controls readout of the memory-stored data on the basis of the degree of compression represented by the compression information in the additional data area of the memory-stored data, when reading out the memory-stored data from the memory.

Abstract: The purpose of the invention is to reduce the amount of copying of information elements generated when renaming a physical register. With respect to information elements stored in logic registers, this computation device stores, in a third logic register, a third element group that includes information elements representing computation results related to vector operations between portions of a first element group that have a predetermined vector length and portions of a second element group that have a predetermined vector length, the first element group and the second element group being groups of information elements stored in a first logic register and second logic register, respectively. The number of regions in which the information elements can be stored simultaneously and which are provided in the physical registers storing the first element group, the second element group, and the third element group is two or less.

Abstract: A vector processor includes: a temporary storage device configured to retain a plurality of elements representing data used at the time of performing an operation appropriate for an instruction; a data type determining part configured to determine what data type the elements retained by the temporary storage device are to be handled as among predetermined data types, in accordance with the instruction; and an output destination deciding part configured to decide an output destination of each of the elements stored by the temporary storage device, based on the result of determination by the data type determining part. The vector processor is configured to output each of the elements to the output destination decided by the output destination deciding part, thereby performing the operation.

Abstract: A repeater includes input ports for inputting packets from modules, input buffers configured to store the input packets, output ports for outputting packets to modules, output buffers configured to store the packets before output, a switch connected between the input buffers and the output buffers, and a controller. The controller selects any of the input buffers, acquires any of the packets from the selected input buffer, and based on a result of comparison between a destination of a packet previously transferred to the output buffer corresponding to the destination of the acquired packet and the destination of the acquired packet and on the availability of the output buffer, determines propriety of transfer of the acquired packet. The controller controls the switch to transfer the packet determined to be transferable, from the input buffer to the output buffer.

Abstract: A vector processor includes: a temporary storage device configured to retain a plurality of elements representing data used at the time of performing an operation appropriate for an instruction; a data type determining part configured to determine what data type the elements retained by the temporary storage device are to be handled as among predetermined data types, in accordance with the instruction; and an output destination deciding part configured to decide an output destination of each of the elements stored by the temporary storage device, based on the result of determination by the data type determining part. The vector processor is configured to output each of the elements to the output destination decided by the output destination deciding part, thereby performing the operation.

Abstract: A repeater includes input ports for inputting packets from modules, input buffers configured to store the input packets, output ports for outputting packets to modules, output buffers configured to store the packets before output, a switch connected between the input buffers and the output buffers, and a controller. The controller selects any of the input buffers, acquires any of the packets from the selected input buffer, and based on a result of comparison between a destination of a packet previously transferred to the output buffer corresponding to the destination of the acquired packet and the destination of the acquired packet and on the availability of the output buffer, determines propriety of transfer of the acquired packet. The controller controls the switch to transfer the packet determined to be transferable, from the input buffer to the output buffer.