Patents by Inventor Kei Kurosawa

Kei Kurosawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5106774
    Abstract: A dynamic random access memory is disclosed which includes a trench type memory cell having a transistor formed in a semiconductive substrate, and a capacitor arranged in a trench formed in the substrate and having a trench structure. The capacitor includes an impurity-doped semiconductive layer formed on the substrate so as to surround the trench and having a conductivity type opposite to that of the substrate, a first capacitor electrode formed in the trench, and a second capacitor electrode having a portion insulatively stacked with said first capacitor electrode in the trench.
    Type: Grant
    Filed: February 4, 1991
    Date of Patent: April 21, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuhiko Hieda, Fumio Horiguchi, Takeshi Hamamoto, Akihiro Nitayama, Kazumasa Sunouchi, Kei Kurosawa, Fujio Masuoka
  • Patent number: 4951175
    Abstract: A dynamic random access memory with a stacked capacitor cell structure is disclosed which has a memory cell provided on a silicon substrate and having a MOSFET and a capacitor. An insulative layer is formed on the substrate, and a first polycrystalline silicon layer is formed on this insulative layer. These layers are simultaneously subjected to etching and define a contact hole which penetrates them to come in contact with the surface of the source. A second polycrystalline silicon layer is formed on the first polycrystalline silicon layer to uniformly cover the inner wall of the contact hole and that surface portion of the source which is exposed through the contact hole. The first and second silicon layers are simultaneously subjected to patterning to provide the lower electrode of the capacitor.
    Type: Grant
    Filed: May 18, 1989
    Date of Patent: August 21, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kei Kurosawa, Hidehiro Watanabe, Shizuo Sawada
  • Patent number: 4874719
    Abstract: Disclosed is a method for making connection between conductor layers through a contact via comprising the steps of (a) forming a first conductive pattern on a semiconductor substrate, (b) forming an insulation interlayer so that it covers the first conductive pattern, (c) forming, on the insulation interlayer, a conductive film of which a second conductive pattern is formed, (d) forming a contact hole, at a predetermined location, in both the conductive film and the insulation interlayer, so that the contact hole reaches the first conductive pattern, (e) forming the conductive layer at least in the contact hole, to make an electrical connection between the conductive film and the first conductive pattern, and (f) subsequent to the formation of the conductive film by step (e), selectively etching the conductive film and the conductive layer, to form said second conductive pattern.
    Type: Grant
    Filed: July 18, 1988
    Date of Patent: October 17, 1989
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kei Kurosawa
  • Patent number: 4505025
    Abstract: A method for manufacturing a semiconductor device is disclosed which comprises the step of forming one or more first grooves by selectively etching a field region of a semiconductor substrate, the step of forming, on the entire surface of the substrate including the first groove, a first insulating film having a thickness substantially equal to or greater than the depth of the first groove, this first insulating film having on its upper surface one or more second grooves corresponding to the first groove, at least one of the second grooves having a width greater than its depth, the step of selectively forming, in at least one of the second grooves having a width greater than its depth, a second insulating film having a thickness substantially equal to the depth of the second groove, the step of forming a third insulating film having a flat surface on its whole surface, the step of applying an anisotropic dry etching technique to the resultant structure to expose the surface of the substrate, thereby obtaining
    Type: Grant
    Filed: May 23, 1983
    Date of Patent: March 19, 1985
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Kei Kurosawa, Fumio Horiguchi
  • Patent number: 4504333
    Abstract: A semiconductor device wherein an oxide film constituting a field region is buried in a semiconductor substrate to make the surface of the field region flush with the top surface of an element region, which is characterized in that another insulating film is buried between the oxide film and the element region. Said another insulating film allows the formation of a larger contact hole.A method for manufacturing such a semiconductor device which is characterized in making use of V-grooves formed in a lift-off process.
    Type: Grant
    Filed: June 4, 1982
    Date of Patent: March 12, 1985
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventor: Kei Kurosawa
  • Patent number: 4497108
    Abstract: A method of manufacturing a semiconductor device wherein a thickness of an insulating film at a peripheral portion of an element formation region of a semiconductor substrate is increased. The feature of this method is that an antioxidant film is formed on the element formation region and subsequently said semiconductor substrate is exposed to an oxygen atmosphere, thereby locally oxidizing that portion of the film which surrounds said element formation region.
    Type: Grant
    Filed: May 17, 1983
    Date of Patent: February 5, 1985
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventor: Kei Kurosawa
  • Patent number: 4472874
    Abstract: A method for manufacturing integrated circuit devices wherein semiconductor elements are isolated by insulation material comprising the following steps of: (a) providing a mask pattern on a predetermined semiconductor element region of a semiconductor substrate; (b) introducing by first ion-implantation impurities of the same conductivity type as that of the substrate into the substrate using the mask pattern as an ion-implantation mask; (c) etching the substrate and forming a groove using the mask pattern as an etching mask in a manner that part of the impurities remain at least under the mask pattern in the side walls of the groove; (d) introducing by second ion-implantation impurities of the same conductivity type as that of the substrate through the groove into the substrate; (e) burying insulation material in the groove; and (f) forming a semiconductor element on the predetermined semiconductor element region.
    Type: Grant
    Filed: June 3, 1982
    Date of Patent: September 25, 1984
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Kei Kurosawa, Tadashi Shibata
  • Patent number: 4407851
    Abstract: A method of forming a flat field region in a semiconductor substrate, which comprises forming a recess in the substrate, forming a covering on the whole surface of the substrate with a first insulating film such as plasma CVD SiO.sub.
    Type: Grant
    Filed: December 29, 1981
    Date of Patent: October 4, 1983
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Kei Kurosawa, Tadashi Shibata
  • Patent number: 4371407
    Abstract: A method for producing a semiconductor device comprises the steps of:forming a first material film on a semiconductor substrate;forming a second material film on said first material film;selectively removing said second material film;exposing a structure thus formed to a gas plasma atmosphere to form a plasma polymerization film on at least an exposed surface of said first material film;removing a remainder of said second material film; andremoving the exposed surface of said first material film by using said plasma polymerization film as a mask to form a first material film pattern.
    Type: Grant
    Filed: October 28, 1981
    Date of Patent: February 1, 1983
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventor: Kei Kurosawa