Patents by Inventor Kei-Leong Ho

Kei-Leong Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7494885
    Abstract: According to one exemplary embodiment, a method for forming a field effect transistor on a substrate comprises a step of forming disposable spacers adjacent to a gate stack situated on the substrate, where the disposable spacers comprise amorphous carbon. The disposable spacers can be formed by depositing a layer of amorphous carbon on the gate stack and anisotropically etching the layer of amorphous carbon. The method further comprises forming source and drain regions in the substrate, where the source and drain regions are situated adjacent to the disposable spacers. According to this exemplary embodiment, the method further comprises removing the disposable spacers, where the removal of the disposable spacers causes substantially no gouging in the substrate. The disposable spacers can be removed by using a dry etch process. The method can further comprise forming extension regions in the substrate adjacent to the gate stack prior to forming the disposable spacers.
    Type: Grant
    Filed: April 5, 2004
    Date of Patent: February 24, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mario M. Pelella, Darin A. Chan, Kei-Leong Ho, Lu You
  • Patent number: 6670227
    Abstract: For fabricating a first device within a core region and a second device within a periphery region, of a semiconductor substrate, disposable spacers having a first width are formed at sidewalls of a first gate stack of the core region and a second gate stack of the periphery region. Drain and source junctions of the second device are formed in the periphery region to the sides of the disposable spacers of the second gate stack. The disposable spacers are removed and permanent spacers having a second width are formed at the sidewalls of the first and second gate stacks, with the second width being less than the first width. Silicide is formed with an exposed portion of a drain bit line junction within the core region after forming the permanent spacers.
    Type: Grant
    Filed: February 10, 2003
    Date of Patent: December 30, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Hsiao-Han Thio, Kei-Leong Ho