Patents by Inventor Kei SHIRAISHI
Kei SHIRAISHI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230317178Abstract: A semiconductor memory device includes a comparator that outputs a signal switched in synchronism with a read enable signal from outside and outputs the signal, and a correction circuit that adjusts the duty cycle of the signal. The correction circuit includes a variable current source connected to a first output portion of the comparator, and a variable current source connected to a second output portion of the comparator, and adjusts the amounts of current output from the current sources to adjust the duty cycles of signals.Type: ApplicationFiled: August 5, 2022Publication date: October 5, 2023Applicant: Kioxia CorporationInventors: Yousuke HAGIWARA, Kei SHIRAISHI
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Patent number: 11568935Abstract: A semiconductor storage device including an output pad, a first circuit connected to the output pad, a second circuit connected to the first circuit, a third circuit configured to output a first setting signal for controlling the first circuit accordance with a characteristic variation of the first circuit, and a fourth circuit configured to generate a second setting signal for controlling the second circuit in accordance with the first setting signal received from the third circuit and output the second setting signal to the second circuit.Type: GrantFiled: May 25, 2021Date of Patent: January 31, 2023Assignee: Kioxia CorporationInventors: Kazuhiko Satou, Ryo Fukuda, Masaru Koyanagi, Kensuke Yamamoto, Masato Dome, Kei Shiraishi, Junya Matsuno, Kenro Kubota
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Publication number: 20230018613Abstract: A semiconductor device includes a first circuit configured to receive a first signal, and output a first voltage to a first node in accordance with a voltage of the first signal being at a first level and output a second voltage to the first node in accordance with the voltage of the first signal being at a second level, the first voltage being higher than the second voltage. A second circuit is coupled to the first node and is configured to latch data based on a voltage of the first node; and a third circuit is coupled to the first node and is configured to output a third voltage to the first node while the first circuit is outputting the first voltage to the first node, and to output a fourth voltage to the first node while the first circuit is outputting the second voltage to the first node, the third voltage being lower than the first voltage, and the fourth voltage being higher than the second voltage.Type: ApplicationFiled: September 26, 2022Publication date: January 19, 2023Applicant: Kioxia CorporationInventors: Junya MATSUNO, Kenro KUBOTA, Masato DOME, Kensuke YAMAMOTO, Kei SHIRAISHI, Kazuhiko SATOU, Ryo FUKUDA, Masaru KOYANAGI
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Patent number: 11495308Abstract: According to an embodiment, a semiconductor device includes a first circuit, a second circuit, and a third circuit. The first circuit is configured to receive a first signal, and output a first voltage to a first node in accordance with a voltage of the first signal being at a first level and output a second voltage to the first node in accordance with the voltage of the first signal being at a second level. The first voltage is higher than the second voltage. The second circuit is coupled to the first node and configured to latch data based on a voltage of the first node. The third circuit includes a first inverter. The first inverter includes a first input terminal coupled to the first node and a first output terminal coupled to the first node.Type: GrantFiled: March 16, 2021Date of Patent: November 8, 2022Assignee: KIOXIA CORPORATIONInventors: Junya Matsuno, Kenro Kubota, Masato Dome, Kensuke Yamamoto, Kei Shiraishi, Kazuhiko Satou, Ryo Fukuda, Masaru Koyanagi
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Patent number: 11450390Abstract: In a semiconductor integrated circuit, an input circuit includes an input and an output stage electrically connected to the input stage via a first node and a second node. The input stage includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first time constant adjusting circuit, and a second time constant adjusting circuit. The first transistor includes a gate that receives an input signal. The second transistor includes a gate that receives a reference signal. The third transistor is disposed adjacent to a drain of the first transistor. The fourth transistor is disposed adjacent to a drain of the second transistor. The first time constant adjusting circuit is electrically connected between a gate of the third transistor and the first node. The second time constant adjusting circuit is electrically connected between a gate of the fourth transistor and the second node.Type: GrantFiled: December 11, 2020Date of Patent: September 20, 2022Assignee: Kioxia CorporationInventors: Fumiya Watanabe, Masaru Koyanagi, Yutaka Shimizu, Yasuhiro Hirashima, Kei Shiraishi, Mikihiko Ito
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Publication number: 20220093188Abstract: According to an embodiment, a semiconductor device includes a first circuit, a second circuit, and a third circuit. The first circuit is configured to receive a first signal, and output a first voltage to a first node in accordance with a voltage of the first signal being at a first level and output a second voltage to the first node in accordance with the voltage of the first signal being at a second level. The first voltage is higher than the second voltage. The second circuit is coupled to the first node and configured to latch data based on a voltage of the first node. The third circuit includes a first inverter. The first inverter includes a first input terminal coupled to the first node and a first output terminal coupled to the first node.Type: ApplicationFiled: March 16, 2021Publication date: March 24, 2022Applicant: Kioxia CorporationInventors: Junya MATSUNO, Kenro KUBOTA, Masato DOME, Kensuke YAMAMOTO, Kei SHIRAISHI, Kazuhiko SATOU, Ryo FUKUDA, Masaru KOYANAGI
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Publication number: 20220059165Abstract: A semiconductor storage device including an output pad, a first circuit connected to the output pad, a second circuit connected to the first circuit, a third circuit configured to output a first setting signal for controlling the first circuit accordance with a characteristic variation of the first circuit, and a fourth circuit configured to generate a second setting signal for controlling the second circuit in accordance with the first setting signal received from the third circuit and output the second setting signal to the second circuit.Type: ApplicationFiled: May 25, 2021Publication date: February 24, 2022Applicant: Kioxia CorporationInventors: Kazuhiko SATOU, Ryo FUKUDA, Masaru KOYANAGI, Kensuke YAMAMOTO, Masato DOME, Kei SHIRAISHI, Junya MATSUNO, Kenro KUBOTA
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Patent number: 11211130Abstract: A semiconductor device comprises an input circuit that includes a first comparator configured to output a first output signal and a second output signal having a phase opposite to that of the first output signal, based on a comparison result of a first input signal and a second input signal which is a complementary signal of the first input signal. A duty ratio of the first output signal and a duty ratio of the second output signal are different from a duty ratio of the first input signal and a duty ratio of the second input signal, respectively.Type: GrantFiled: May 5, 2020Date of Patent: December 28, 2021Assignee: KIOXIA CORPORATIONInventors: Yasuhiro Hirashima, Masaru Koyanagi, Mikihiko Ito, Kei Shiraishi, Fumiya Watanabe
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Publication number: 20210295930Abstract: According to one embodiment, in a semiconductor integrated circuit, an input circuit has an input and an output stage electrically connected to the input stage via a first node and a second node. The input stage includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first time constant adjusting circuit and a second time constant adjusting circuit. The first transistor has a gate that receives an input signal. The second transistor has a gate that receives a reference signal. The third transistor is disposed adjacent to a drain of the first transistor. The fourth transistor is disposed adjacent to a drain of the second transistor. The first time constant adjusting circuit is electrically connected between a gate of the third transistor and the first node. The second time constant adjusting circuit is electrically connected between a gate of the fourth transistor and the second node.Type: ApplicationFiled: December 11, 2020Publication date: September 23, 2021Applicant: Kioxia CorporationInventors: Fumiya WATANABE, Masaru KOYANAGI, Yutaka SHIMIZU, Yasuhiro HIRASHIMA, Kei SHIRAISHI, Mikihiko ITO
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Patent number: 10847232Abstract: A semiconductor memory device includes a differential waveform shaping circuit including first and waveform shaping circuits connected in parallel. The first waveform shaping circuit has a first inverting amplifier, and two inverters connected in series. The first inverting amplifier inverts and differentially amplifies an input signal having a rectangular waveform. Then, the output of the first inverting amplifier is passed through the two inverters. The second waveform shaping circuit has a first inverter, a second inverting amplifier, and a second inverter connected in series. The second inverting amplifier inverts and differentially amplifies the output signal from the first invertor, and the second inverter inverts the output signal from the second inverting amplifier. The differential waveform shaping circuit generates an output signal by averaging the output signal from the first waveform shaping circuit and the output signal from the second waveform shaping circuit.Type: GrantFiled: August 29, 2019Date of Patent: November 24, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Kei Shiraishi, Masaru Koyanagi, Mikihiko Ito, Yumi Takada, Yasuhiro Hirashima, Satoshi Inoue, Kensuke Yamamoto, Shouichi Ozaki, Taichi Wakui, Fumiya Watanabe
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Publication number: 20200265902Abstract: A semiconductor device comprises an input circuit that includes a first comparator configured to output a first output signal and a second output signal having a phase opposite to that of the first output signal, based on a comparison result of a first input signal and a second input signal which is a complementary signal of the first input signal. A duty ratio of the first output signal and a duty ratio of the second output signal are different from a duty ratio of the first input signal and a duty ratio of the second input signal, respectively.Type: ApplicationFiled: May 5, 2020Publication date: August 20, 2020Inventors: Yasuhiro HIRASHIMA, Masaru KOYANAGI, Mikihiko ITO, Kei SHIRAISHI, Fumiya WATANABE
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Publication number: 20200202959Abstract: A semiconductor memory device includes a differential waveform shaping circuit including first and waveform shaping circuits connected in parallel. The first waveform shaping circuit has a first inverting amplifier, and two inverters connected in series. The first inverting amplifier inverts and differentially amplifies an input signal having a rectangular waveform. Then, the output of the first inverting amplifier is passed through the two inverters. The second waveform shaping circuit has a first inverter, a second inverting amplifier, and a second inverter connected in series. The second inverting amplifier inverts and differentially amplifies the output signal from the first invertor, and the second inverter inverts the output signal from the second inverting amplifier. The differential waveform shaping circuit generates an output signal by averaging the output signal from the first waveform shaping circuit and the output signal from the second waveform shaping circuit.Type: ApplicationFiled: August 29, 2019Publication date: June 25, 2020Inventors: Kei SHIRAISHI, Masaru KOYANAGI, Mikihiko ITO, Yumi TAKADA, Yasuhiro HIRASHIMA, Satoshi INOUE, Kensuke YAMAMOTO, Shouichi OZAKI, Taichi WAKUI, Fumiya WATANABE
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Patent number: 10679710Abstract: A semiconductor device comprises an input circuit that includes a first comparator configured to output a first output signal and a second output signal having a phase opposite to that of the first output signal, based on a comparison result of a first input signal and a second input signal which is a complementary signal of the first input signal. A duty ratio of the first output signal and a duty ratio of the second output signal are different from a duty ratio of the first input signal and a duty ratio of the second input signal, respectively.Type: GrantFiled: September 2, 2018Date of Patent: June 9, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yasuhiro Hirashima, Masaru Koyanagi, Mikihiko Ito, Kei Shiraishi, Fumiya Watanabe
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Patent number: 10482977Abstract: A semiconductor memory device includes a first transistor including a first end connected to a first pad and a second end connected to a first node, a second transistor including a first end connected to a second pad and a second end connected to the first node, a third transistor including a first end connected to the second pad, a second end connected to the first node, and a gate connected to a second node and having a size different from that of the second transistor, a fourth transistor including a first end connected to the first pad, a second end connected to the second node, and a gate connected to the first node, and a fifth transistor including a first end connected to the second pad, a second end connected to the second node, and a gate connected to the first node.Type: GrantFiled: March 5, 2018Date of Patent: November 19, 2019Assignee: TOSHIBA MEMEORY CORPORATIONInventors: Kei Shiraishi, Masaru Koyanagi, Mikihiko Ito, Yasuhiro Hirashima
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Publication number: 20190295661Abstract: A semiconductor device comprises an input circuit that includes a first comparator configured to output a first output signal and a second output signal having a phase opposite to that of the first output signal, based on a comparison result of a first input signal and a second input signal which is a complementary signal of the first input signal. A duty ratio of the first output signal and a duty ratio of the second output signal are different from a duty ratio of the first input signal and a duty ratio of the second input signal, respectively.Type: ApplicationFiled: September 2, 2018Publication date: September 26, 2019Inventors: Yasuhiro HIRASHIMA, Masaru KOYANAGI, Mikihiko ITO, Kei SHIRAISHI, Fumiya WATANABE
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Publication number: 20190080769Abstract: A semiconductor memory device includes a first transistor including a first end connected to a first pad and a second end connected to a first node, a second transistor including a first end connected to a second pad and a second end connected to the first node, a third transistor including a first end connected to the second pad, a second end connected to the first node, and a gate connected to a second node and having a size different from that of the second transistor, a fourth transistor including a first end connected to the first pad, a second end connected to the second node, and a gate connected to the first node, and a fifth transistor including a first end connected to the second pad, a second end connected to the second node, and a gate connected to the first node.Type: ApplicationFiled: March 5, 2018Publication date: March 14, 2019Inventors: Kei SHIRAISHI, Masaru KOYANAGI, Mikihiko ITO, Yasuhiro HIRASHIMA
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Patent number: 9912898Abstract: According to an embodiment, an amplifier which amplifies a first signal to output a second signal includes the following elements. The comparator compares the first signal with a third signal to output a fourth signal. The delay circuit delays a fifth signal by a delay time to generate a sixth signal. The first capacitor is connected between a voltage source and a first node that provides the third signal. The second capacitor is connected between the first node and a second node that provides the second signal. The first switch is connected between the second node and a constant current source, and is controlled by the fourth signal and the fifth signal. The second switch is connected between the first node and the second node, and is controlled by the fifth signal and the sixth signal.Type: GrantFiled: September 3, 2016Date of Patent: March 6, 2018Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Yasuhiro Shinozuka, Masanori Furuta, Kei Shiraishi
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Publication number: 20170070695Abstract: According to an embodiment, an amplifier which amplifies a first signal to output a second signal includes the following elements. The comparator compares the first signal with a third signal to output a fourth signal. The delay circuit delays a fifth signal by a delay time to generate a sixth signal. The first capacitor is connected between a voltage source and a first node that provides the third signal. The second capacitor is connected between the first node and a second node that provides the second signal. The first switch is connected between the second node and a constant current source, and is controlled by the fourth signal and the fifth signal. The second switch is connected between the first node and the second node, and is controlled by the fifth signal and the sixth signal.Type: ApplicationFiled: September 3, 2016Publication date: March 9, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yasuhiro SHINOZUKA, Masanori FURUTA, Kei SHIRAISHI
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Patent number: 9312873Abstract: An analog-to-digital converter has a sampler to hold a sampled signal, an input signal predictor to generate a prediction signal at predetermined timing before a signal level of a ramp signal that monotonically increases or monotonically decreases with time crosses a signal level of the sampled signal, a comparator to compare signal levels of the ramp signal and the sampled signal to output a comparison signal showing whether the signal level of the ramp signal is larger than the signal lever of the sampled signal, a first counter to perform a count operation in synchronism with a first clock signal within a period from start of a comparison operation by the comparator to generation of the prediction signal, and a second counter to perform a count operation in synchronism with a second clock signal.Type: GrantFiled: January 5, 2015Date of Patent: April 12, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Masanori Furuta, Kei Shiraishi, Yasuhiro Shinozuka
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Patent number: 9240797Abstract: According to an embodiment, a power supply noise cancelling circuit includes a generator, a first multiplier, a subtractor and a digital-to-analog converter. The generator generates a sine wave signal. The first multiplier multiplies a digital input signal by a digital signal based on the sine wave signal to generate a first digital product signal. The subtractor subtracts a digital signal based on the first digital product signal from the digital input signal to generate a digital difference signal. The digital-to-analog converter performs a digital-to-analog conversion on the digital difference signal to obtain an analog output signal.Type: GrantFiled: March 13, 2015Date of Patent: January 19, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Kei Shiraishi, Masanori Furuta, Junya Matsuno, Tetsuro Itakura