Patents by Inventor Kei Tanihira

Kei Tanihira has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11830920
    Abstract: A semiconductor device includes a semiconductor part including a first semiconductor layer of a first conductivity type; a first electrode provided on a back surface of the semiconductor part; and a second electrode provided on a front surface of the semiconductor part. The second electrode includes a barrier layer and a metal layer. The barrier layer contacts the first semiconductor layer and including vanadium or a vanadium compound as a major component. The metal layer is provided on the barrier layer.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: November 28, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Naofumi Hirata, Tomomi Kuraguchi, Shinichi Ueki, Yoichi Hori, Kei Tanihira
  • Publication number: 20230299211
    Abstract: A semiconductor device includes a first electrode, a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a fourth semiconductor layer, a fifth semiconductor layer, and a second electrode. The fourth semiconductor layer is located in a second region on the first semiconductor layer. The fourth semiconductor layer is separated from the second semiconductor layer with a portion of the first semiconductor layer interposed. An impurity concentration of the fourth semiconductor layer is greater than an impurity concentration of the first semiconductor layer and less than an impurity concentration of the second semiconductor layer.
    Type: Application
    Filed: August 4, 2022
    Publication date: September 21, 2023
    Inventors: Kei TANIHIRA, Yoichi HORI, Hiroshi KONO
  • Patent number: 11508854
    Abstract: A semiconductor device includes a first electrode, a first semiconductor region connected to the first electrode and being of a first conductivity type, a second semiconductor region provided on the first semiconductor region, contacting the first semiconductor region and being of a second conductivity type, first metal layers and second metal layers provided on the second semiconductor region and contacting the second semiconductor region, a third semiconductor region provided between the first semiconductor region and the first metal layer, and a second electrode. The third semiconductor region contacts the first and second semiconductor regions and being of the first conductivity type. An impurity concentration of the third semiconductor region is greater than an impurity concentration of the first semiconductor region. The second electrode contacts the first semiconductor region, the second semiconductor region, the first metal layers, and the second metal layers.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: November 22, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Kei Tanihira, Yoichi Hori
  • Publication number: 20220293762
    Abstract: A semiconductor device includes a semiconductor part including a first semiconductor layer of a first conductivity type; a first electrode provided on a back surface of the semiconductor part; and a second electrode provided on a front surface of the semiconductor part. The second electrode includes a barrier layer and a metal layer. The barrier layer contacts the first semiconductor layer and including vanadium or a vanadium compound as a major component. The metal layer is provided on the barrier layer.
    Type: Application
    Filed: August 19, 2021
    Publication date: September 15, 2022
    Inventors: Naofumi HIRATA, Tomomi KURAGUCHI, Shinichi UEKI, Yoichi HORI, Kei TANIHIRA
  • Publication number: 20210376168
    Abstract: A semiconductor device includes a first electrode, a first semiconductor region connected to the first electrode and being of a first conductivity type, a second semiconductor region provided on the first semiconductor region, contacting the first semiconductor region and being of a second conductivity type, first metal layers and second metal layers provided on the second semiconductor region and contacting the second semiconductor region, a third semiconductor region provided between the first semiconductor region and the first metal layer, and a second electrode. The third semiconductor region contacts the first and second semiconductor regions and being of the first conductivity type. An impurity concentration of the third semiconductor region is greater than an impurity concentration of the first semiconductor region. The second electrode contacts the first semiconductor region, the second semiconductor region, the first metal layers, and the second metal layers.
    Type: Application
    Filed: February 17, 2021
    Publication date: December 2, 2021
    Inventors: Kei Tanihira, Yoichi Hori