Abstract: A plurality of first selectors are connected to a branch condition taken/non-taken decision circuit, and a second selector is connected to the first selector. Among branch condition taken/non-taken signals, at least one signal is common to the first selectors. Consequently, the step number of microinstruction to realize a macroinstructions is decreased, and the executing time of the macroinstruction is shortened.

Abstract: In a division circuit, a dividend register (7) and a remainder register (14) are connected so that a bit in the MSB of the former is shifted to the LSB of the latter. Higher bits of an N-bit divisor are monitored by a detector (18) and a zero-detect (ZD) signal is generated when they are all "0"s. In the presence of the ZD signal, subtraction is performed by an N/2-bit subtractor (28) between lower-bit data of a divisor and data in the remainder register and, in the absence of the ZD signal, first subtraction is performed between lower-bit data of the divisor and higher-bit data of the dividend register (7) and second subtraction is performed between higher-bit data of the divisor register and data in the remainder register (14). A "1" is written into the LSB of the dividend register (7) either in response to a "1" in the MSB of the remainder register (14) or when no borrow results from subtractions.