Patents by Inventor Kei-Yu Ko

Kei-Yu Ko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6537922
    Abstract: An etchant including C2HxFy, where x is an integer from two to five, inclusive, where y is an integer from one to four, inclusive, and where x plus y equals six. The etchant etches doped silicon dioxide with selectivity over both undoped silicon dioxide and silicon nitride. Thus, undoped silicon dioxide and silicon nitride may be employed as etch stops in dry etch processes which utilize the C2HxFy-containing etchant. C2HxFy may be employed as either a primary etchant or as an additive to another etchant or etchant mixture.
    Type: Grant
    Filed: July 25, 2000
    Date of Patent: March 25, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Kei-Yu Ko, Li Li, Guy T. Blalock
  • Publication number: 20030042465
    Abstract: Processes, etchants, and apparatus useful for etching an insulating oxide layer of a substrate without damaging underlying nitride features or field oxide regions. The processes exhibit good selectivity to both nitrides and field oxides. Integrated circuits produced utilizing etching processes of the present invention are much less likely to be defective due to photoresist mask misalignment. Etchants used in processes of the present invention comprise a carrier gas, one or more C2+F gases, CH2F2, and a gas selected from the group consisting of CHF3, CF4, and mixtures thereof. The processes can be performed at power levels lower than what is currently utilized in the prior art.
    Type: Application
    Filed: August 30, 2001
    Publication date: March 6, 2003
    Applicant: Micron Technology, Inc.
    Inventor: Kei-yu Ko
  • Patent number: 6479864
    Abstract: Disclosed is a semiconductor structure including a plurality of gate stacks that is fabricated by a process of using undoped silicon dioxide as an etch mask for selectively etching doped silicon dioxide. In one embodiment, a doped silicon dioxide layer is formed over a semiconductor substrate. An undoped silicon dioxide layer is formed and patterned over the doped silicon dioxide layer. Doped silicon dioxide is selectively removed from the doped silicon dioxide layer through the pattern by use of a plasma etch or another suitable etch that removes doped silicon dioxide at a rate greater than that of undoped silicon dioxide. The process may be used to form contacts to the semiconductor substrate. The process may also be used to form a structure with a lower and an upper series of parallel gate stacks, where the gate stacks have upper surfaces consisting essentially of undoped silicon dioxide.
    Type: Grant
    Filed: May 25, 2000
    Date of Patent: November 12, 2002
    Assignee: Micron Technology Inc.
    Inventor: Kei-Yu Ko
  • Patent number: 6458685
    Abstract: A bulk semiconductor substrate is provided which has an active area received between at least two undoped silicon dioxide comprising substrate isolation regions. The substrate includes at least two transistor gate constructions received at least partially over the active area. The gate constructions include gates having their sides and tops covered with insulating material comprising at least one of undoped silicon dioxide and silicon nitride. A doped silicon dioxide layer is formed over the active area, the isolation regions and the gate constructions. A patterned masking layer is formed over the doped silicon dioxide layer. The patterned masking layer has a mask opening formed therein which overlaps at least one of the gate constructions and the active area. The substrate is placed within a high density plasma etcher. The etcher has a directly coolable top power electrode, a biasable electrostatic chuck, a focus ring, and directly heatable chamber sidewalls.
    Type: Grant
    Filed: May 17, 2001
    Date of Patent: October 1, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Kei-Yu Ko, Dave Pecora
  • Patent number: 6444586
    Abstract: Disclosed is a process for removing doped silicon dioxide from a structure selectively to undoped silicon dioxide. A structure having both doped and undoped silicon dioxide regions is exposed to a high density plasma etch having a fluorinated etch chemistry. Doped silicon dioxide is preferably removed thereby at a rate 10 times or more greater than that of undoped silicon dioxide. The etch is conducted in a chamber having an upper electrode to which a source power is applied and a lower electrode to which a bias power is applied sufficient to generate a power density on a surface of the structure such that the source power density is in a range less than or equal to about 1000 W per 200-mm diameter wafer surface. The high density plasma etch has an ion density not less that about 109 ions/cm3. A variety of structures are formed with the etch process, including self-aligned contacts to a semiconductor substrate.
    Type: Grant
    Filed: August 17, 2001
    Date of Patent: September 3, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Kei-Yu Ko
  • Patent number: 6432833
    Abstract: A method includes placing a certain substrate within a high density plasma etcher. The etcher has a directly heatable top electrode having separately powerable inner and outer components, a biasable electrostatic chuck, and a directly heatable focus ring. Plasma etching is conducted through a mask on the substrate, using a hydrogen containing fluorocarbon chemistry, with power on both the top electrode components together totalling less than or equal to 1000 W per 200 mm of substrate diameter, with an electrostatic chuck bias power less than the total top electrode power, with the top electrode heated to greater than 100° C. and the focus ring heated to at least 200° C. Such etching is conducted into a doped oxide on the substrate substantially selective to insulating material on the substrate to form a substantially self-aligned contact opening to a substrate location beneath a doped silicon dioxide layer on the substrate. Other implementations are contemplated.
    Type: Grant
    Filed: December 20, 1999
    Date of Patent: August 13, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Kei-Yu Ko
  • Patent number: 6337285
    Abstract: The invention is a two-step dual-chemistry process for etching through a selected portion of an insulating oxide layer of a substrate to create a self-aligned contact opening without damaging underlying field oxide regions. The first etching step uses essentially a CxFy (x>1)-type chemistry that etches only partially through the oxide layer, since it has very good selectivity to the silicon nitride cap of the gate stacks but a poor selectivity to the field oxide regions. The second etching step employs a second chemistry comprising an H-containing fluorocarbon chemistry. The second chemistry has a good selectivity to the field oxide regions and, at the same time, is able to finish etching the opening.
    Type: Grant
    Filed: March 21, 2000
    Date of Patent: January 8, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Kei-Yu Ko
  • Publication number: 20010053609
    Abstract: Disclosed is a process for removing doped silicon dioxide from a structure selectively to undoped silicon dioxide. A structure having both doped and undoped silicon dioxide regions is exposed to a high density plasma etch having a fluorinated etch chemistry. Doped silicon dioxide is preferably removed thereby at a rate 10 times or more greater than that of undoped silicon dioxide. The etch is conducted in a chamber having an upper electrode to which a source power is applied and a lower electrode to which a bias power is applied sufficient to generate a power density on a surface of the structure such that the source power density is in a range less than or equal to about 1000 W per 200-mm diameter wafer surface. The high density plasma etch has an ion density not less that about 109 ions/cm3. A variety of structures are formed with the etch process, including self-aligned contacts to a semiconductor substrate.
    Type: Application
    Filed: August 17, 2001
    Publication date: December 20, 2001
    Inventor: Kei-Yu Ko
  • Publication number: 20010029097
    Abstract: A bulk semiconductor substrate is provided which has an active area received between at least two undoped silicon dioxide comprising substrate isolation regions. The substrate includes at least two transistor gate constructions received at least partially over the active area. The gate constructions include gates having their sides and tops covered with insulating material comprising at least one of undoped silicon dioxide and silicon nitride. A doped silicon dioxide layer is formed over the active area, the isolation regions and the gate constructions. A patterned masking layer is formed over the doped silicon dioxide layer. The patterned masking layer has a mask opening formed therein which overlaps at least one of the gate constructions and the active area. The substrate is placed within a high density plasma etcher. The etcher has a directly coolable top power electrode, a biasable electrostatic chuck, a focus ring, and directly heatable chamber sidewalls.
    Type: Application
    Filed: May 17, 2001
    Publication date: October 11, 2001
    Inventors: Kei-Yu Ko, Dave Pecora
  • Patent number: 6277758
    Abstract: Disclosed is a process for removing doped silicon dioxide from a structure selectively to undoped silicon dioxide. A structure having both doped and undoped silicon dioxide regions is exposed to a high density plasma etch having a fluorinated etch chemistry. Doped silicon dioxide is preferably removed thereby at a rate 10 times or more greater than that of undoped silicon dioxide. The etch is conducted in a chamber having an upper electrode to which a source power is applied and a lower electrode to which a bias power is applied sufficient to generate a power density on a surface of the structure such that the source power density is in a range less than or equal to about 1000 W per 200-mm diameter wafer surface. The high density plasma etch has an ion density not less that about 109 ions/cm3. A variety of structures are formed with the etch process, including self-aligned contacts to a semiconductor substrate.
    Type: Grant
    Filed: July 23, 1998
    Date of Patent: August 21, 2001
    Assignee: Micron Technology, Inc.
    Inventor: Kei-Yu Ko
  • Patent number: 6121671
    Abstract: An etchant including C.sub.2 H.sub.x F.sub.y, where x is an integer from two to five, inclusive, where y is an integer from one to four, inclusive, and where x plus y equals six. The etchant etches doped silicon dioxide with selectivity over both undoped silicon dioxide and silicon nitride. Thus, undoped silicon dioxide and silicon nitride may be employed as etch stops in dry etch processes which utilize the C.sub.2 H.sub.x F.sub.y -containing etchant. C.sub.2 H.sub.x F.sub.y may be employed as either a primary etchant or as an additive to another etchant or etchant mixture. The invention also includes semiconductor devices that include structures that have been patterned with an etchant of the present invention or in accordance with the method of the present invention. Specifically, the present invention includes semiconductor devices including doped silicon oxide structures with substantially vertical sidewalls and adjacent undoped silicon oxide or silicon nitride structures exposed adjacent the sidewall.
    Type: Grant
    Filed: January 13, 1999
    Date of Patent: September 19, 2000
    Assignee: Micron Technology, Inc.
    Inventors: Kei-Yu Ko, Li Li, Guy T. Blalock
  • Patent number: 6117791
    Abstract: An etchant including C.sub.2 H.sub.x F.sub.y, where x is an integer from two to five, inclusive, where y is an integer from one to four, inclusive, and where x plus y equals six. The etchant etches doped silicon dioxide with selectivity over both undoped silicon dioxide and silicon nitride. Thus, undoped silicon dioxide and silicon nitride may be employed as etch stops in dry etch processes which utilize the C.sub.2 H.sub.x F.sub.y -containing etchant. C.sub.2 H.sub.x F.sub.y may be employed as either a primary etchant or as an additive to another etchant or etchant mixture.
    Type: Grant
    Filed: June 22, 1998
    Date of Patent: September 12, 2000
    Assignee: Micron Technology, Inc.
    Inventors: Kei-Yu Ko, Li Li, Guy T. Blalock
  • Patent number: 6117788
    Abstract: Etching methods are described. In one embodiment, a first layer of first material is formed over a semiconductor substrate, and a second layer of second material is formed over the first layer. The second layer is selectively etched relative to the first layer, with the etching thereof taking place within a dual source, high density plasma etcher having a source powered at less than or equal to about 300 Watts, a bias power of less than or equal to about 300 Watts, and a pressure greater than or equal to about 10 mTorr. In another embodiment, a first undoped oxide layer is formed over a substrate, and a second doped oxide layer is formed over the first layer. The second doped oxide layer is etched selectively relative to the first undoped layer, with etching taking place within a dual source, high density plasma etcher wherein one of the sources is an inductive source powered at less than or equal to about 300 Watts.
    Type: Grant
    Filed: September 1, 1998
    Date of Patent: September 12, 2000
    Assignee: Micron Technology, Inc.
    Inventor: Kei-Yu Ko
  • Patent number: 5399900
    Abstract: A semiconductor device having in a body of a group III-V semiconductor material at least one isolation region which is stable at temperatures up to about 900.degree. C. The isolation region is formed of ions of a group III or V element which are implanted into the body and then thermally annealed at a temperature of between 650.degree. C. and 900.degree. C. This provides the regions with voids which remove free carriers and makes the region highly resistive.
    Type: Grant
    Filed: October 8, 1993
    Date of Patent: March 21, 1995
    Assignee: Eastman Kodak Company
    Inventors: Kei-Yu Ko, Samuel Chen, Shuit-Tong Lee