Patents by Inventor Keichiro Takeda

Keichiro Takeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Nonvolatile semiconductor memory with testing circuit
    Patent number: 6434068
    Abstract: A semiconductor memory circuit of the present invention comprises a word line, a bit line, a memory cell transistor having a first terminal applied to a first electrical potential, a second terminal connected to said bit line and a gate connected to the word line, a reference bit line, a reference cell transistor having a first terminal applied to the first electrical potential, a second terminal connected to the reference bit line and a gate connected to the word line, a sense node electrically connected to the bit line, a reference node electrically connected to the reference bit line, a differential amplifier having a first input connected to the sense node, a second input connected to the reference node and an output, a first load circuit connected between the sense node and a second potential source, a second load circuit connected between the reference node and the second potential source and a test circuit receiving a test signal. The first load circuit has a first resistance value.
    Type: Grant
    Filed: September 20, 2001
    Date of Patent: August 13, 2002
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Teruhiro Harada, Keichiro Takeda
  • Nonvolatile semiconductor memory with testing circuit
    Publication number: 20020021605
    Abstract: A semiconductor memory circuit of the present invention comprises a word line, a bit line, a memory cell transistor having a first terminal applied to a first electrical potential, a second terminal connected to said bit line and a gate connected to the word line, a reference bit line, a reference cell transistor having a first terminal applied to the first electrical potential, a second terminal connected to the reference bit line and a gate connected to the word line, a sense node electrically connected to the bit line, a reference node electrically connected to the reference bit line, a differential amplifier having a first input connected to the sense node, a second input connected to the reference node and an output, a first load circuit connected between the sense node and a second potential source, a second load circuit connected between the reference node and the second potential source and a test circuit receiving a test signal. The first load circuit has a first resistance value.
    Type: Application
    Filed: September 20, 2001
    Publication date: February 21, 2002
    Inventors: Teruhiro Harada, Keichiro Takeda