Patents by Inventor Keigo Aoki
Keigo Aoki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150089527Abstract: Included is a unit configured to calculate feature points of a scene image of a screen acquired from a television program that is currently on air on a given number of broadcast stations, or a simulcast distribution server at predetermined intervals, and save, in a storage unit, feature point data of a predetermined time period on a broadcast station basis; a unit configured to receive feature point data of an image of a television program currently being watched by a user, the feature point data having been transmitted from a mobile terminal of the user; and a unit configured to check the received feature point data against the feature point data saved in the storage unit and identify a scene image that satisfies a predetermined matching condition.Type: ApplicationFiled: September 25, 2014Publication date: March 26, 2015Inventors: Hiroyuki Matsuyama, Keigo Aoki, Sakae Takeuchi, Setsuo Kimura
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Patent number: 8587699Abstract: A solid state imaging device including: a pixel portion having a plurality of pixels arrayed two-dimensionally and including an effective pixel portion and a dummy pixel portion; a timing generator for generating address information for reading signals of pixels of the pixel portion and timing signals for reading; a column decoder; a column selection circuit for generating transfer signals and reset signals used for control for reading signals of pixels in the column portions of the pixel portion by the plurality of line selection signals output from the column decoder based on the timing signals and selecting column portions of pixels in an effective portion and a dummy portion of the pixel portion; and a transfer circuit for reading signals of corresponding pixels based on the transfer signals and reset signals output from the column selection circuit, then transferring signals of read pixels by the row signal lines.Type: GrantFiled: November 30, 2010Date of Patent: November 19, 2013Assignee: Sony CorporationInventor: Keigo Aoki
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Patent number: 8421979Abstract: A drive IC chip (21) including a circuit for driving a display region (41) is mounted on a panel substrate (11). An anisotropic conductive film (31) is interposed between the panel substrate (11) and the drive IC chip (21) and electrically connects the bump electrodes (22) of the drive IC chip (21) and the electrode pads (27) of the panel substrate (11). The anisotropic conductive film (31) is arranged to extend beyond all side surfaces (21b to 21d) other than one specific side surface (21a) of the drive IC chip (21).Type: GrantFiled: May 21, 2009Date of Patent: April 16, 2013Assignee: Sharp Kabushiki KaishaInventors: Yukio Shimizu, Takashi Matsui, Motoji Shiota, Keigo Aoki, Hiroki Nakahama
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Publication number: 20120133876Abstract: A region for mounting components such as an IC chip is sufficiently ensured on a glass substrate with which a liquid crystal panel is configured, without reducing the number of panel pieces to be taken from a large panel. A liquid crystal panel is composed of a first glass substrate (10) and a second glass substrate (20) which face each other with a liquid crystal therebetween. The first glass substrate (10) and the second glass substrate (20) are formed in substantially the same size in plan view and bonded together in a state in which these substrates are shifted from each other by a predetermined distance in the direction of the longer side or in the direction of the shorter side. Regions to become a frame (frame regions) are provided on both the first glass substrate (10) and the second glass substrate (20), and pads (60) are provided on both of these frame regions.Type: ApplicationFiled: January 15, 2010Publication date: May 31, 2012Applicant: SHARP KABUSHIKI KAISHAInventors: Hiroki Nakahama, Keigo Aoki, Gen Nagaoka, Kiyoshi Inada, Motoji Shiota
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Publication number: 20110122337Abstract: A drive IC chip (21) including a circuit for driving a display region (41) is mounted on a panel substrate (11). An anisotropic conductive film (31) is interposed between the panel substrate (11) and the drive IC chip (21) and electrically connects the bump electrodes (22) of the drive IC chip (21) and the electrode pads (27) of the panel substrate (11). The anisotropic conductive film (31) is arranged to extend beyond all side surfaces (21b to 21d) other than one specific side surface (21a) of the drive IC chip (21).Type: ApplicationFiled: May 21, 2009Publication date: May 26, 2011Applicant: SHARP KABUSHIKI KAISHAInventors: Yukio Shimizu, Takashi Matsui, Motoji Shiota, Keigo Aoki, Hiroki Nakahama
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Publication number: 20110069213Abstract: A solid state imaging device including: a pixel portion having a plurality of pixels arrayed two-dimensionally and including an effective pixel portion and a dummy pixel portion; a timing generator for generating address information for reading signals of pixels of the pixel portion and timing signals for reading; a column decoder; a column selection circuit for generating transfer signals and reset signals used for control for reading signals of pixels in the column portions of the pixel portion by the plurality of line selection signals output from the column decoder based on the timing signals and selecting column portions of pixels in an effective portion and a dummy portion of the pixel portion; and a transfer circuit for reading signals of corresponding pixels based on the transfer signals and reset signals output from the column selection circuit, then transferring signals of read pixels by the row signal lines.Type: ApplicationFiled: November 30, 2010Publication date: March 24, 2011Applicant: SONY CORPORATIONInventor: Keigo Aoki
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Patent number: 7852386Abstract: A solid state imaging device including: a pixel portion having a plurality of pixels arrayed two-dimensionally and including an effective pixel portion and a dummy pixel portion; a timing generator for generating address information for reading signals of pixels of the pixel portion and timing signals for reading; a column decoder; a column selection circuit for generating transfer signals and reset signals used for control for reading signals of pixels in the column portions of the pixel portion by the plurality of line selection signals output from the column decoder based on the timing signals and selecting column portions of pixels in an effective portion and a dummy portion of the pixel portion; and a transfer circuit for reading signals of corresponding pixels based on the transfer signals and reset signals output from the column selection circuit, then transferring signals of read pixels by the row signal lines.Type: GrantFiled: March 2, 2006Date of Patent: December 14, 2010Assignee: Sony CorporationInventor: Keigo Aoki
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Publication number: 20060203112Abstract: A solid state imaging device including: a pixel portion having a plurality of pixels arrayed two-dimensionally and including an effective pixel portion and a dummy pixel portion; a timing generator for generating address information for reading signals of pixels of the pixel portion and timing signals for reading; a column decoder; a column selection circuit for generating transfer signals and reset signals used for control for reading signals of pixels in the column portions of the pixel portion by the plurality of line selection signals output from the column decoder based on the timing signals and selecting column portions of pixels in an effective portion and a dummy portion of the pixel portion; and a transfer circuit for reading signals of corresponding pixels based on the transfer signals and reset signals output from the column selection circuit, then transferring signals of read pixels by the row signal lines.Type: ApplicationFiled: March 2, 2006Publication date: September 14, 2006Inventor: Keigo Aoki
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Patent number: 5327267Abstract: A dielectric display device includes a pair of substrates, at least one of which is transparent, spaced in parallel a constant distance apart, and facing each other. A dielectric display material is inserted between the pair of substrates. Further, a pair of electrodes, at least one of which includes a plurality of line (or scanning) electrodes, are disposed on the sides of the substrate facing the other substrate. Finally, a static erasing conductor is disposed extending peripherally along, and spaced a constant distance from, the ends of the electrodes for preventing intrusion of static electricity into electric lead lines.Type: GrantFiled: December 1, 1992Date of Patent: July 5, 1994Assignee: Sharp Kabushiki KaishaInventors: Keigo Aoki, Yoshinao Ohnuma