Abstract: A vertical repetition of a unit layer stack includes an insulating layer, a first sacrificial material layer, another insulating layer, and a second sacrificial material layer. A memory opening is formed through the vertical repetition, and a memory opening fill structure is formed in the memory opening. A backside trench is formed through the alternating stack. The first sacrificial material layers are replaced with first electrically conductive layers, and the second sacrificial material layer are replaced with second electrically conductive layers after formation of the first electrically conductive layers.

Abstract: A vertical repetition of a unit layer stack includes an insulating layer, a first sacrificial material layer, another insulating layer, and a second sacrificial material layer. A memory opening is formed through the vertical repetition, and a memory opening fill structure is formed in the memory opening. A backside trench is formed through the alternating stack. The first sacrificial material layers are replaced with first electrically conductive layers, and the second sacrificial material layer are replaced with second electrically conductive layers after formation of the first electrically conductive layers.

Abstract: Devices are formed on a substrate. A first-tier alternating stack of first insulating layers and first spacer material layers having first stepped surfaces and a first retro-stepped dielectric material portion are formed over the substrate. A sacrificial contact via structure is formed through the first retro-stepped dielectric material portion. A second-tier alternating stack of second insulating layers and second spacer material layers is formed with second stepped surfaces. A second retro-stepped dielectric material portion including a doped silicate glass liner and a silicate glass material portion is formed over the second stepped surfaces. Memory stack structures are formed through the second-tier alternating stack and the first-tier alternating stack. A contact via cavity is formed down to the sacrificial contact via structure. The doped silicate glass liner is recessed and the sacrificial contact via structure is removed, to form a contact via structure in the contact via cavity.

Abstract: A method of forming a three-dimensional memory device includes forming an alternating stack of in-process composite layers and sacrificial material layers including a lower insulating layer, a sacrificial spacer layer including silicon nitride or a semiconductor material, and an upper insulating layer, forming a memory opening vertically extending through the vertical stack, forming a memory opening fill structure in the memory opening, the memory opening fill structure including an in-process memory film and a vertical semiconductor channel, forming backside trenches through the alternating stack, replacing the sacrificial material layers with electrically conductive layers by removing the sacrificial material layers to form backside recesses and by depositing an electrically conductive material in the backside recesses, and converting the in-process composite layers into composite insulating layers by removing the sacrificial spacer layers to form lateral cavities and by optionally depositing replacement di

Abstract: Devices are formed on a substrate. A first-tier alternating stack of first insulating layers and first spacer material layers having first stepped surfaces and a first retro-stepped dielectric material portion are formed over the substrate. A sacrificial contact via structure is formed through the first retro-stepped dielectric material portion. A second-tier alternating stack of second insulating layers and second spacer material layers is formed with second stepped surfaces. A second retro-stepped dielectric material portion including a doped silicate glass liner and a silicate glass material portion is formed over the second stepped surfaces. Memory stack structures are formed through the second-tier alternating stack and the first-tier alternating stack. A contact via cavity is formed down to the sacrificial contact via structure. The doped silicate glass liner is recessed and the sacrificial contact via structure is removed, to form a contact via structure in the contact via cavity.

Abstract: A three-dimensional memory device includes a first-tier structure containing a first alternating stack of first insulating layers and first electrically conductive layers that has first stepped surfaces, and a first retro-stepped dielectric material portion contacting the first stepped surfaces of the first alternating stack, and a second-tier structure containing a second alternating stack of second insulating layers and second electrically conductive layers that has second stepped surfaces, and a second retro-stepped dielectric material portion contacting the second stepped surfaces of the second alternating stack. The first retro-stepped dielectric material portion has a higher etch rate than the second retro-stepped dielectric material portion. Memory stack structures vertically extend through the first alternating stack and the second alternating stack. Each of the memory stack structures includes a memory film and a vertical semiconductor channel.

Abstract: A three-dimensional memory device includes a first-tier structure containing a first alternating stack of first insulating layers and first electrically conductive layers that has first stepped surfaces, and a first retro-stepped dielectric material portion contacting the first stepped surfaces of the first alternating stack, and a second-tier structure containing a second alternating stack of second insulating layers and second electrically conductive layers that has second stepped surfaces, and a second retro-stepped dielectric material portion contacting the second stepped surfaces of the second alternating stack. The first retro-stepped dielectric material portion has a higher etch rate than the second retro-stepped dielectric material portion. Memory stack structures vertically extend through the first alternating stack and the second alternating stack. Each of the memory stack structures includes a memory film and a vertical semiconductor channel.

Abstract: An alternating stack of insulating layers and sacrificial material layers including stepped surfaces is formed over a substrate. After formation of a retro-stepped dielectric material portion over the stepped surfaces, an array of cylindrical openings is formed through the retro-stepped dielectric material portion and the alternating stack. A continuous cavity is formed by isotropically etching the insulating layers and the retro-stepped dielectric material portion selective to the sacrificial material layers. Remaining portions of the retro-stepped dielectric material portion include dielectric pillar structures. A continuous fill material portion is formed in the continuous cavity. Memory stack structures are formed through the alternating stack. The sacrificial material layers and the dielectric pillar structures are replaced with combinations of an electrically conductive layer and a contact via structure. The contact via structures are self-aligned to the electrically conductive layers.

Abstract: In an LDMOS transistor, a channel length is reduced to increase a saturation current without causing an off-state breakdown voltage optimized in terms of trade-off between an on-resistance and the off-state breakdown voltage. A short channel region is selectively formed between an element isolation film and a low-concentration body region in which a channel is formed such that the short channel region is located immediately below a gate oxide film. The short channel region has a conduction type opposite to that of the low-concentration body region and has a carrier concentration higher than that of the low-concentration body region. The body region is retreated by the presence of the short channel region toward a high-concentration source region.

Abstract: In an LDMOS transistor, a channel length is reduced to increase a saturation current without causing an off-state breakdown voltage optimized in terms of trade-off between an on-resistance and the off-state breakdown voltage. A short channel region is selectively formed between an element isolation film and a low-concentration body region in which a channel is formed such that the short channel region is located immediately below a gate oxide film. The short channel region has a conduction type opposite to that of the low-concentration body region and has a carrier concentration higher than that of the low-concentration body region. The body region is retreated by the presence of the short channel region toward a high-concentration source region.

Abstract: There is provided a high withstand voltage LDMOS which is a MOS transistor formed on a semiconductor substrate and isolated by a trench, and a source region of which is sandwiched by a drain region, in which the metal layer gate wire connected to the gate electrode is led out outside the trench so as to pass over a P-type drift layer.