Patents by Inventor Keigo Ootani

Keigo Ootani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8072257
    Abstract: A booster circuit includes first and second transistors, a first capacitor, a first drive circuit, a second capacitor, a first controller, and a second controller. The first and second transistors are connected in series between a first voltage and a second voltage. One end of the first capacitor is connected to a connection node between the first transistor and the second transistor. The first drive circuit boosts the voltage at the other end of the first capacitor. The second capacitor is connected between the second voltage and a reference voltage. The first controller controls conduction/non-conduction of the first transistor. The second controller inputs any of the first voltage and the second voltage to the second transistor, and thereby controls conduction/non-conduction of the second transistor. The boost circuit is supplied with the reference voltage, a supply voltage, and a boost clock signal, and generates the second voltage by boosting the supply voltage.
    Type: Grant
    Filed: October 6, 2009
    Date of Patent: December 6, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Keigo Ootani, Takashi Tahata
  • Publication number: 20100085111
    Abstract: A booster circuit includes first and second transistors, a first capacitor, a first drive circuit, a second capacitor, a first controller, and a second controller. The first and second transistors are connected in series between a first voltage and a second voltage. One end of the first capacitor is connected to a connection node between the first transistor and the second transistor. The first drive circuit boosts the voltage at the other end of the first capacitor. The second capacitor is connected between the second voltage and a reference voltage. The first controller controls conduction/non-conduction of the first transistor. The second controller inputs any of the first voltage and the second voltage to the second transistor, and thereby controls conduction/non-conduction of the second transistor. The boost circuit is supplied with the reference voltage, a supply voltage, and a boost clock signal, and generates the second voltage by boosting the supply voltage.
    Type: Application
    Filed: October 6, 2009
    Publication date: April 8, 2010
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Keigo Ootani, Takashi Tahata
  • Publication number: 20100002021
    Abstract: A method of driving a display panel is provided. The display panel includes a first scan group including first to third scan lines, and a plurality of data lines which intersect the first to third scan lines, and first display cells of a first color which are connected with the first scan line, second display cells of a second color which are connected with the second scan line, third display cells of a third color which are connected with the third scan line. The method is achieved by precharging the data lines to a predetermined voltage in a first horizontal period; and by supplying a data signal to the first to third display cells through the data lines driving of the first to third display cells after the data lines are precharged in the first horizontal period. In the driving of the first to third display cells, one of the first to third display cells corresponding to one of said first to third colors, having a maximum spectral luminous efficacy, is first driven.
    Type: Application
    Filed: June 26, 2009
    Publication date: January 7, 2010
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Yoshiharu Hashimoto, Keigo Ootani
  • Patent number: 7633332
    Abstract: A boosting circuit includes a boosting capacitor to which an input voltage is applied; a smoothing capacitor to which a boosted voltage is applied; a discharging MOS transistor configured to connect said boosting capacitor and said smoothing capacitor in a discharging operation during a boosting operation period such that charge stored in said boosting capacitor is discharged to said smoothing capacitor; and a charging MOS transistor configured to apply the input voltage to said boosting capacitor in a charging operation during the boosting operation period to charge up said charging capacitor. A back gate of said charging MOS transistor and a back gate of said discharging MOS transistor are connected to a common node, and said common node is connected to different voltages in the charging operation and the discharging operation.
    Type: Grant
    Filed: July 7, 2008
    Date of Patent: December 15, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Keigo Ootani
  • Publication number: 20090009237
    Abstract: A boosting circuit includes a boosting capacitor to which an input voltage is applied; a smoothing capacitor to which a boosted voltage is applied; a discharging MOS transistor configured to connect said boosting capacitor and said smoothing capacitor in a discharging operation during a boosting operation period such that charge stored in said boosting capacitor is discharged to said smoothing capacitor; and a charging MOS transistor configured to apply the input voltage to said boosting capacitor in a charging operation during the boosting operation period to charge up said charging capacitor. A back gate of said charging MOS transistor and a back gate of said discharging MOS transistor are connected to a common node, and said common node is connected to different voltages in the charging operation and the discharging operation.
    Type: Application
    Filed: July 7, 2008
    Publication date: January 8, 2009
    Applicant: NEC Electronics Corporation
    Inventor: Keigo Ootani
  • Publication number: 20070236435
    Abstract: A display apparatus drives a data line on a time division basis. In this process, the data line is driven twice, namely in two modes: a precharge mode and a drive mode. Before the drive mode in which a drive voltage according to display data is supplied to a data line among a set of data lines to be driven on a time division basis, a precharge voltage is supplied at least to a data line adjacent to the data line individually.
    Type: Application
    Filed: April 6, 2007
    Publication date: October 11, 2007
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Kiyoshi Miyazaki, Keigo Ootani, Hidekazu Nagato