Abstract: The disclosure includes bus wiring constituted by wiring lines; a gradation voltage generation circuit that generates M gradation voltages representing brightness levels with M gradations, and applies the M gradation voltages to an intermediate portion on M wiring lines belonging to the bus wiring; a plurality of decoders, each of which receives M gradation voltages via the M wiring lines and selects one of the M gradation voltages according to the pixel data pieces to output the selected gradation voltage; a plurality of output amplifiers that individually amplifies the voltages output from the plurality of decoders and generates the amplified voltages as the plurality of pixel drive voltages; and first and second inter-gradation short circuits that short-circuit one ends of each of the M wiring lines and the other ends of each of the M wiring lines according to a load signal for capturing the pixel data pieces.

Abstract: The disclosure includes bus wiring constituted by wiring lines; a gradation voltage generation circuit that generates M gradation voltages representing brightness levels with M gradations, and applies the M gradation voltages to an intermediate portion on M wiring lines belonging to the bus wiring; a plurality of decoders, each of which receives M gradation voltages via the M wiring lines and selects one of the M gradation voltages according to the pixel data pieces to output the selected gradation voltage; a plurality of output amplifiers that individually amplifies the voltages output from the plurality of decoders and generates the amplified voltages as the plurality of pixel drive voltages; and first and second inter-gradation short circuits that short-circuit one ends of each of the M wiring lines and the other ends of each of the M wiring lines according to a load signal for capturing the pixel data pieces.

Abstract: Display apparatuses, data drivers and display controller are provided. The data drivers receive video signals, generate positive-polarity and negative-polarity gradation data signals with respect to a predetermined reference voltage based on the video signals, output the positive-polarity gradation data signals to one of a first and a second data line groups, and output the negative-polarity gradation data signals to the other data line group. The data drivers generate, as the positive-polarity gradation data signals, signals in which data pulses each having a positive-polarity analog voltage value corresponding to a luminance level of each pixel based on the video signal appear in predetermined cycles, and generate, as the negative-polarity gradation data signals, signals where data pulses each having a negative-polarity analog voltage value corresponding to a luminance level of each pixel appear in each predetermined cycle with phases different from the positive-polarity gradation data signals.

Abstract: The disclosure includes bus wiring constituted by wiring lines; a gradation voltage generation circuit that generates M gradation voltages representing brightness levels with M gradations, and applies the M gradation voltages to an intermediate portion on M wiring lines belonging to the bus wiring; a plurality of decoders, each of which receives M gradation voltages via the M wiring lines and selects one of the M gradation voltages according to the pixel data pieces to output the selected gradation voltage; a plurality of output amplifiers that individually amplifies the voltages output from the plurality of decoders and generates the amplified voltages as the plurality of pixel drive voltages; and first and second inter-gradation short circuits that short-circuit one ends of each of the M wiring lines and the other ends of each of the M wiring lines according to a load signal for capturing the pixel data pieces.

Abstract: The disclosure includes bus wiring constituted by wiring lines; a gradation voltage generation circuit that generates M gradation voltages representing brightness levels with M gradations, and applies the M gradation voltages to an intermediate portion on M wiring lines belonging to the bus wiring; a plurality of decoders, each of which receives M gradation voltages via the M wiring lines and selects one of the M gradation voltages according to the pixel data pieces to output the selected gradation voltage; a plurality of output amplifiers that individually amplifies the voltages output from the plurality of decoders and generates the amplified voltages as the plurality of pixel drive voltages; and first and second inter-gradation short circuits that short-circuit one ends of each of the M wiring lines and the other ends of each of the M wiring lines according to a load signal for capturing the pixel data pieces.

Abstract: Display apparatuses, data drivers and display controller are provided. The data drivers receive video signals, generate positive-polarity and negative-polarity gradation data signals with respect to a predetermined reference voltage based on the video signals, output the positive-polarity gradation data signals to one of a first and a second data line groups, and output the negative-polarity gradation data signals to the other data line group. The data drivers generate, as the positive-polarity gradation data signals, signals in which data pulses each having a positive-polarity analog voltage value corresponding to a luminance level of each pixel based on the video signal appear in predetermined cycles, and generate, as the negative-polarity gradation data signals, signals where data pulses each having a negative-polarity analog voltage value corresponding to a luminance level of each pixel appear in each predetermined cycle with phases different from the positive-polarity gradation data signals.

Abstract: A level shifter circuit includes a first voltage conversion circuit and a second voltage conversion circuit. The first voltage conversion circuit receives an input signal having an amplitude ranging between a power supply potential (GND) and a power supply potential (VDDL), a power supply potential (VDDH) which is higher than the power supply potential (VDDL) is supplied. Further, a current limiting circuit is provided that limits a current supplied from a power supply line of the power supply potential (VDDH), and outputs a voltage signal with a larger amplitude than that of the input signal according to the input signal. The second voltage conversion circuit is supplied with the power supply potential (VDDH, and outputs an output signal with an amplitude ranging between the power supply potential GND and the power supply potential (VDDH).

Abstract: A level shifter circuit according to the present invention includes a first voltage conversion circuit and a second voltage conversion circuit. The first voltage conversion circuit receives an input signal having an amplitude ranging between a power supply potential GND and a power supply potential VDDL, a power supply potential VDDH which is higher than the power supply potential VDDL is supplied. Further, a current limiting circuit is provided that limits a current supplied from a power supply line of the power supply potential VDDH, and outputs a voltage signal with a larger amplitude than that of the input signal according to the input signal. The second voltage conversion circuit is supplied with the power supply potential VDDH, and outputs an output signal with an amplitude ranging between the power supply potential GND and the power supply potential VDDH.